We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman Spectroscopy (muRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

The design of wafer processing equipment needs to continuously evolve and respond to the challenges of the future. In this article, we present the evolution of rapid thermal processing (RTP) in the transistor manufacturing environment with emphasis on production-worthy performance over a temperature regime that addresses the sub-400degC processing requirements. Temperature and thermal budget control is increasingly critical for contact material processing for sub-65 nm nodes. We present low temperature spike anneal as an application to address thermal budget challenges and demonstrate the extendibility of lamp-based RTP to low temperature processes