The video anomaly detection (VAD) aims to automatically analyze spatiotemporal patterns in surveillance videos collected from open spaces to detect anomalous events that may cause harm, such as fighting, stealing, and car accidents. However, vision-based surveillance systems such as closed-circuit television (CCTV) often capture personally identifiable information. The lack of transparency and interpretability in video transmission and usage raises public concerns about privacy and ethics, limiting the real-world application of VAD. Recently, researchers have focused on privacy concerns in VAD by conducting systematic studies from various perspectives, including data, features, and systems, making privacy-preserving VAD (P2VAD) a hotspot in the AI community. However, the current research in P2VAD is fragmented, and prior reviews have mostly focused on methods using RGB sequences, overlooking privacy leakage and appearance bias considerations. To address this gap, this article is the first to systematically review the progress of P2VAD, defining its scope and providing an intuitive taxonomy. We outline the basic assumptions, learning frameworks, and optimization objectives of various approaches, analyzing their strengths, weaknesses, and potential correlations. In addition, we provide open access to research resources such as benchmark datasets and available code. Finally, we discuss key challenges and future opportunities from the perspectives of AI development and P2VAD deployment, aiming to the guide future work in the field.

The rapid advancement of quantum computing has ushered in a new era of post-quantum cryptography, urgently demanding quantum-resistant digital signatures to secure modern communications and transactions. Among NIST-standardized candidates, Falcon stands out because it is a compact lattice-based signature scheme suitable for size-sensitive applications. In this paper, we present cuFalcon, a high-throughput GPU implementation of Falcon that addresses its computational bottlenecks through adaptive parallel strategies. At the operational level, we optimize Falcon key components for GPU architectures through memory-efficient FFT, adaptive parallel ffSampling, and a compact computation mode. For signature-level optimization, to improve scalability across different GPU architectures, we implement three versions of cuFalcon: the raw key version, the expanded key version, and the balanced version. Additionally, we design batch processing, streaming mechanisms, and memory pooling to handle multiple signature tasks efficiently. Ultimately, performance evaluations show significant improvements, with the raw key version achieving 172 k signatures per second and the expanded key version reaching 201 k. Compared to the raw key version, the balanced version achieves a 7% improvement in throughput, while compared to the expanded key version, it reduces memory usage by 70%. Furthermore, our raw key version implementation outperforms the reference implementation by 36.74 & times; and achieves a 2.71 & times; speedup over the state-of-the-art GPU implementation.

As the Internet of Things (IoT) continues to expand into mission-critical and long-lived applications, securing low-power wide-area networks (LPWANs) such as Narrowband IoT (NB-IoT) against both classical and quantum threats becomes imperative. Existing NB-IoT security mechanisms terminate at the core network, leaving transmission payloads exposed. This paper proposes HySecure, an FPGA-based hybrid cryptographic platform that integrates both classical elliptic curve and post-quantum schemes to achieve end-to-end (E2E) security for NB-IoT communication. Our architecture, built upon the lightweight RISC-V PULPino platform, incorporates hardware accelerators for X25519, Kyber, Ed25519, and Dilithium. We design a hybrid key establishment protocol combining ECDH and Kyber through HKDF, and a dual-signature scheme using EdDSA and Dilithium to ensure authenticity and integrity during handshake. Cryptographic functions are evaluated on FPGA, achieving a 32.2× to 145.4× speedup. NS-3 simulations under realistic NB-IoT configurations demonstrate acceptable latency and throughput for the proposed hybrid schemes, validating their practicality for secure constrained IoT deployments and communications.

Machine Learning as a Service (MLaaS) become a popular application in cloud-based services, where users upload their data to a service provider and the provider runs a pre-learned model to give predictions back. However, MLaaS has a risk of privacy leakage cause the data transferred may contain users’ sensitive information. Homomorphic Encryption (HE) is a promising way to handle this problem. It allows the server to make calculations directly on encrypted data, and so guarantees the confidentiality of data. Unluckily, inference on encrypted data usually has massive time consumption and high memory requirement. To solve this problem, we propose Mini-batching to increase the batch utilization of ciphertext, which allows adjustment to models’ performance levels. Each level has its time cost, memory requirement, and classification capacity, indicating the number of images classified per inference. Additionally, we design a protocol called Simulating ReLU via Homomorphic Encryption (SRHE) to implement the real ReLU function on ciphertext which proved to be suitable for deeper neural networks. In the experiment, we implement our model Noya on MNIST and CIFAR-10 datasets for six performance levels and achieves 99(76)

Security and privacy are critical in cloud-based Internet of Things (IoT) and Artificial Intelligence of Things (AIoT) applications. As quantum computing advances, post-quantum cryptography (PQC) has emerged as a key technology for ensuring security in future IoT and AIoT architectures. SPHINCS+, a leading post-quantum signature algorithm, has been selected by the National Institute of Standards and Technology (NIST) as one of the next-generation signature standards. However, due to its complex structure and extensive hash operations, SPHINCS+ suffers from slower signature generation and verification compared to other post-quantum algorithms. Consequently, accelerating SPHINCS+ is essential for adapting it to IoT environments. This article presents a compute unified device architecture (CUDA)-based Batch Parallel optimization of SPHINCS+ (CBPSPX), which fully utilizes the computing resources of NVIDIA graphics processing units (GPUs) to enhance the performance of SPHINCS+. Specifically, we propose the thread utilization efficiency index (TUEI), which can be used to theoretically evaluate the effectiveness of various parallel methods. Then, we propose an intrablock batch processing model that dynamically adjusts parallel task scales within a block to optimize throughput, making it particularly suitable for IoT scenarios requiring high-throughput large-scale device authentication. Meanwhile, we divide the signature generation process into three subprocesses and adopt different parallel strategies based on the thread requirements of each subprocess to maximize the value of TUEI. For the signature verification process, we propose a columnar storage strategy to replace the traditional row storage structure, which significantly improves the performance of batch signature verification. Experimental results indicate that our SPHINCS+ implementations across all three parameter sets are better than previous optimized GPU-based implementations and achieve speedups of 1.4x to 2.5x for signature generation and 4.6x to 11.3x for signature verification on GPU RTX 3090.

Private information retrieval (PIR) is a key building block in many privacy-preserving systems, such as database querying, cloud computing and the Internet of Things. Homomorphic encryption (HE) is a promising solution for PIR. Although it has great potential, its practicality for keyword PIR is relatively low due to its high computational overhead. In this paper, we propose an efficient keyword PIR protocol called BCPIR, based on block code. In BCPIR, we design a new mapping scheme based on linear block codes that maps keywords to blocked binary strings with only one significant bit per block. Our block code can determine the distribution interval of significant bits and reduce the randomness of the significant bit distribution after mapping. In addition, based on block code, we preprocess the database and propose a novel keyword comparison method, which can support batch comparison and greatly improve the efficiency. We compare our solution to previous work and find that our solution is on average over 142 times faster for larger databases over 128MB. To further increase the utility of our solution, our scheme can be further accelerated on GPU. We test it on an A100 GPU and the overall performance can be increased by a further 10–20 times.

Bit-wise Fully Homomorphic Encryption schemes like FHEW and TFHE offer efficient functional bootstrapping, enabling concurrent function evaluation and noise reduction. While advantageous for secure computations, these schemes suffer from high data expansion, posing significant performance challenges in practical ap- plications due to massive ciphertexts. To address these issues, we propose VeloFHE, a CUDA-accelerated design to enhance the efficiency of FHEW and TFHE schemes on GPUs. We develop a novel hybrid four-step Number Theoretic Transform (NTT) approach for fast polynomial multiplication. By decomposing large-scale NTTs into highly parallelizable submodules, incorporating cyclic and negacyclic convolutions, and introducing several memory-oriented optimizations, we significantly reduce both the computational complexity and memory requirements. For blind rotation, besides the gadget decomposition approach, we also apply a recent proposed modulus raising technique to both schemes to alleviate memory pressure. We further optimize it by refining computational flow to reduce noise from scaling and maintain accumulator compatibility. For key switching, we address input-output parallelism mismatches, and offloading suitable computations to the CPU, effectively hiding latency through asynchronous execution. Additionally, we explore batching in bootstrapping, de- veloping a general framework that accommodates both schemes with either gadget decomposition or modulus raising method. Our experimental results demonstrate significant performance improvements. The proposed NTT implementation shows over 35% improvement compared to recent GPU implementations. On an RTX 4090 GPU, we achieve speedups of 371.86x and 390.44x for FHEW and TFHE gate bootstrapping, respectively, compared to OpenFHE running on a 48-thread CPU at a 128-bit security level. The corresponding throughputs are 7,007 and 11,378 operations per second. Furthermore, relative to the state-of-the-art GPU implementation [XLK+25], our approach provides speedups of 2.56x, 2.24x, and 2.33x for TFHE gate bootstrapping, homomorphic evaluation of arbitrary functions, and homomorphic flooring operation, respectively. Our VeloFHE surpasses some current hardware designs, offering an effective solution for more practical and efficient privacy-preserving computations.

The threat posed by quantum computing has precipitated an urgent need for post-quantum cryptography. Recently, the post-quantum digital signature draft FIPS 204 has been published, delineating the details of the ML-DSA, which is derived from the CRYSTALS-Dilithium. Despite these advancements, server environments, especially those equipped with GPU devices necessitating high-throughput signing, remain entrenched in classical schemes. A conspicuous void exists in the realm of GPU implementation or server-specific designs for ML-DSA. In this paper, we propose the first server-oriented GPU design tailored for the ML-DSA signing procedure in high-throughput servers. We introduce several innovative theoretical optimizations to bolster performance, including depth-prior sparse ternary polynomial multiplication, the branch elimination method, and the rejection-prioritized checking order. Furthermore, exploiting server-oriented features, we propose a comprehensive GPU hardware design, augmented by a suite of GPU implementation optimizations to further amplify performance. Additionally, we present variants for sampling sparse polynomials, thereby streamlining our design. The deployment of our implementation on both server-grade and commercial GPUs demonstrates significant speedups, ranging from 284.9x to 485.3x against the CPU baseline, and an improvement of up to 60.9% compared to related work, affirming the effectiveness and efficiency of the proposed GPU architecture for ML-DSA signing procedure.

Post-quantum cryptographic algorithms can resist attacks from quantum computers and address the threat posed by quantum computing to public key cryptography. However, post-quantum key exchange and digital signature protocols consume a significant amount of memory, making it difficult to directly deploy them on embedded IoT devices with limited computing resources and memory space. To address the deployment challenges and limited practicality of post-quantum cryptographic algorithms on embedded devices, we propose an optimized implementation scheme for lattice-based post-quantum cryptographic algorithm NTRU on the RISC-V platform. The aim is to achieve constant-time polynomial convolution operations for NTRU on embedded devices. Firstly, designing computation flows suitable for convolution operations in NTRU. Secondly, proposing a constant-time address correction algorithm and hybrid multiplication techniques to enhance the efficiency of NTRU convolution operations on the RISC-V platform. Finally, based on the concept of product-form polynomials, the generation and computation methods for sparse polynomials are redesigned to support convolution operations using product-form polynomials, thereby reducing the time complexity of polynomial multiplication in NTRU. By comparing clock cycles, this paper’s approach demonstrates a 60

Privacy-preserving machine learning (PPML) demands secure inference on sensitive data in untrusted environments. Fully homomorphic encryption (FHE) enables computation directly on encrypted data, but it incurs prohibitive communication and computational overhead on edge devices. Hybrid homomorphic encryption (HHE) mitigates this by combining symmetric encryption with FHE, reducing client-side costs; however, existing implementations remain impractical for resource-constrained deployments. This paper proposes the first end-to-end hardware-accelerated HHE framework, which integrates a lightweight symmetric cipher optimized for FHE compatibility with a dedicated hardware accelerator. Beyond this integration, we introduce a microarchitectural optimization for throughput and energy efficiency. The proposed architecture is validated within a complete PPML pipeline, demonstrating significantly lower latency and power consumption than software implementations. Experimental results on a PYNQ-Z2 platform with MNIST validate our approach, achieving a 50x reduction in client-side encryption latency and a 2x throughput gain over existing FPGA-based HHE accelerators. These improvements enable practical and secure inference on edge devices. Our contributions establish a hardware-software co-design methodology for deploying scalable, secure machine learning in resourceconstrained environments, validating the feasibility of low-power HHE for edge deployment.

Homomorphic Encryption (HE) enhances data security by enabling computations on encrypted data, advancing privacy-focused computations. The BFV scheme, a promising HE scheme, raises considerable performance challenges. Graphics Processing Units (GPUs), with considerable parallel processing abilities, offer an effective solution. In this work, we present an in-depth study on accelerating and comparing BFV variants on GPUs, including Bajard-Eynard-Hasan-Zucca (BEHZ), Halevi-Polyakov-Shoup (HPS), and recent variants. We introduce a universal framework for all variants, propose optimized BEHZ implementation, and first support HPS variants with large parameter sets on GPUs. We also optimize low-level arithmetic and high-level operations, minimizing instructions for modular operations, enhancing hardware utilization for base conversion, and implementing efficient reuse strategies and fusion methods to reduce computational and memory consumption. Leveraging our framework, we offer comprehensive comparative analyses. Performance evaluation shows a 31.9X speedup over OpenFHE running on a multi-threaded CPU and 39.7% and 29.9% improvement for tensoring and relinearization over the state-of-the-art GPU BEHZ implementation. The leveled HPS variant records up to 4X speedup over other variants, positioning it as a highly promising alternative for specific applications.

In sectors such as finance and healthcare, where data governance is subject to rigorous regulatory requirements, the exchange and utilization of data are particularly challenging. Federated Learning (FL) has risen as a pioneering distributed machine learning paradigm that enables collaborative model training across multiple institutions while maintaining data decentralization. Despite its advantages, FL is vulnerable to adversarial threats, particularly poisoning attacks during model aggregation, a process typically managed by a central server. However, in these systems, neural network models still possess the capacity to inadvertently memorize and potentially expose individual training instances. This presents a significant privacy risk, as attackers could reconstruct private data by leveraging the information contained in the model itself. Existing solutions fall short of providing a viable, privacy-preserving BRFL system that is both completely secure against information leakage and computationally efficient. To address these concerns, we propose Lancelot, an innovative and computationally efficient BRFL framework that employs fully homomorphic encryption (FHE) to safeguard against malicious client activities while preserving data privacy. Our extensive testing, which includes medical imaging diagnostics and widely-used public image datasets, demonstrates that Lancelot significantly outperforms existing methods, offering more than a twenty-fold increase in processing speed, all while maintaining data privacy.

The threat of quantum computing has spurred research into post-quantum cryptography. SQIsign, a candidate submitted to the standardization process of the National Institute of Standards and Technology, is emerging as a promising isogeny-based signature scheme. This work aimed to enhance SQIsign’s practical deployment by optimizing its low-level arithmetic operations. Through hierarchical decomposition and performance profiling, we identified the ideal-to-isogeny translation, primarily involving elliptic curve operations, as the main bottleneck. We developed efficient 32-bit finite field arithmetic for elliptic curves, such as basic operations, like addition with carry, subtraction with borrow, and conditional move. We then implemented arithmetic operations in the Montgomery domain, and extended these to quadratic field extensions. Our implementation offers improved compatibility with 32-bit architectures and enables more fine-grained SIMD acceleration. Performance evaluations demonstrated the practicality in low-level operations. Our work has potential in easing the development of SQIsign in practice, making SQIsign more efficient and practical for real-world post-quantum cryptographic applications.

Digital signatures are fundamental building blocks in various protocols to provide integrity and authenticity. The development of the quantum computing has raised concerns about the security guarantees afforded by classical signature schemes. CRYSTALS-Dilithium is an efficient post-quantum digital signature scheme based on lattice cryptography and has been selected as the primary algorithm for standardization by the National Institute of Standards and Technology. In this work, we present a high-throughput GPU implementation of Dilithium. For individual operations, we employ a range of computational and memory optimizations to overcome sequential constraints, reduce memory usage and IO latency, address bank conflicts, and mitigate pipeline stalls. This results in high and balanced compute throughput and memory throughput for each operation. In terms of concurrent task processing, we leverage task-level batching to fully utilize parallelism and implement a memory pool mechanism for rapid memory access. Considering the impact of varying repetition numbers in Dilithium on the overall execution time and hardware utilization, we propose a dynamic task scheduling mechanism to improve multiprocessor occupancy and significantly reduce execution time. Furthermore, we apply asynchronous computing and launch multiple streams to hide data transfer latencies and maximize the computing capabilities of both CPU and GPU. Across all three security levels, our GPU implementation can concurrently compute ten thousand tasks in less than 32 miliseconds for signing and 15 miliseconds for verification on both commercial and server-grade GPUs. This achieves microsecond-level amortized execution times for each task, offering a high-throughput and quantum-resistant solution suitable for a wide array of applications in real systems.

The development of modern manufacturing has raised greater demands on the accuracy, response speed, and operating cost of industrial accident warnings. Compared to conventional contact sensors, surveillance cameras can contactlessly capture spatial-temporal information of the open workspace with stable data quality, widely used in industrial process monitoring. However, due to the scarcity of industrial video datasets and the rarity and diversity of abnormal events, existing video -based anomaly detection models perform poorly in manufacturing scenarios. In this regard, we collect two datasets from typical industrial sites and propose a memory -enhanced spatial-temporal encoding (MSTE) framework for automatic industrial anomaly detection. The proposed MSTE framework learns spatial and temporal normality as well as spatial-temporal correlations with parallel structures and simultaneously measures deviations in appearance, motion, and consistency to respond to complex industrial anomalies accurately. Experimental results on public benchmarks and realworld industrial videos show that our method outperforms existing methods and achieves accurate temporal localization of various spatial-temporal anomalies, which helps to improve the safety and reliability of intelligent manufacturing.

The rapid development of AI applications powered by deep learning in edge devices boosts the opportunity for real-time health monitoring. To address the potential privacy concern in the inference phase, homomorphic encryption (HE) is an alternative solution that encrypts inference data without exposing raw data and has several distinct advantages, (i.e., single-round communication, lightweight bandwidth consumption, and non-interactive computation). However, the computational overhead on the current HE-based privacy-preserving inference necessitates a substantial amount of time, which is not feasible for some real-time applications on edge devices. To address this issue, we propose CNN-guardian, a unified and compact neural network structure for real-time inference in HE-based inference on edge GPU. CNN-guardian designs a HE-friendly neural network and GPU engine that optimizes HE operations to accelerate the inference in the HE domain.

. Homomorphic Encryption (HE) presents a promising solu-tion to securing neural networks for Machine Learning as a Service (MLaaS). Despite its potential, the real-time applicability of current HE-based solutions remains a challenge, and the diversity in network structures often results in ine ffi cient implementations and maintenance. To address these issues, we introduce a unified and compact network structure for real-time inference in convolutional neural networks based on HE. We further propose several optimization strategies, including an innovative compression and encoding technique and rearrangement in the pixel encoding sequence, enabling a highly e ffi cient batched computation and reducing the demand for time-consuming HE operations. To further expedite computation, we propose a GPU acceleration engine to leverage the massive thread-level parallelism to speed up computations. We test our framework with the MNIST, Fashion-MNIST, and CIFAR-10 datasets, demonstrating accuracies of 99.14%, 90.8%, and 61.09%, respectively. Furthermore, our framework maintains a steady processing speed of 0.46 seconds on a single-thread CPU, and a brisk 31.862 millisec-onds on an A100 GPU for all datasets. This represents an enhancement in speed more than 3000 times compared to pervious work, paving the way for future explorations in the realm of secure and real-time machine learning applications.

The rapid development of AI applications powered by deep learning in edge devices boosts the opportunity for real-time health monitoring. To address the potential privacy concern in the inference phase, homomorphic encryption (HE) is an alternative solution that encrypts inference data without exposing raw data and has several distinct advantages, (i.e., single-round communication, lightweight bandwidth consumption, and non-interactive computation). However, the computational overhead on the current HE-based privacy-preserving inference necessitates a substantial amount of time, which is not feasible for some real-time applications on edge devices. To address this issue, we propose CNN-guardian, a unified and compact neural network structure for real-time inference in HE-based inference on edge GPU. CNN-guardian designs a HE-friendly neural network and GPU engine that optimizes HE operations to accelerate the inference in the HE domain.