In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

As everyone knows that in today's time Artificial Intelligence, Machine Learning and Deep Learning are being used extensively and generally researchers are thinking of using them everywhere. At the same time, we are also seeing that the second wave of corona has wreaked havoc in India. More than 4 lakh cases are coming in 24 h. In the meantime, news came that a new deadly fungus has come, which doctors have named Mucormycosis (Black fungus). This fungus also spread rapidly in many states, due to which states have declared this disease as an epidemic. It has become very important to find a cure for this life-threatening fungus by taking the help of our today's devices and technology such as artificial intelligence, data learning. It was found that the CT-Scan has much more adequate information and delivers greater evaluation validity than the chest X-Ray. After that the steps of Image processing such as pre-processing, segmentation, all these were surveyed in which it was found that accuracy score for the deep features retrieved from the ResNet50 model and SVM classifier using the Linear kernel function was 94.7%, which was the highest of all the findings. Also studied about Deep Belief Network (DBN) that how easy it can be to diagnose a life-threatening infection like fungus. Then a survey explained how computer vision helped in the corona era, in the same way it would help in epidemics like Mucormycosis.

VLSI designers are inspired by the widespread use of portable low power devices. In this paper, a 9T SRAM cell has been analyzed and implemented at 45 nm technology node with Cadence virtuoso tool. The read stability and write ability of considered cell is improved by 2.05 × and 1.13 × in comparison to conventional 6T SRAM cell. The write access time of 9T SRAM cell is 3.37 × and 2.94 × better in comparison of conventional 6T and differential (DF) 8T SRAM cell respectively. Furthermore, the write power of 9T SRAM cell is reduced by a factor of 2.07 × and 1.77 × as comparison of conventional 6T and Differential 8T SRAM cell respectively at 0.5 V supply voltage. The data retention voltage of 9T SRAM cell is better at all corners in comparison of conventional 6T and differential 8T SRAM cell respectively. The 9T SRAM cell may be utilized in IoT based devices such as medical equipments, space applications, etc.

This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of I on /I off ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

In portable electronic devices, SRAM cells play a major role to decide the performance of gadgets. In this paper, a Schmitt trigger-based 9T (ST9T) SRAM cell is simulated at 45nm technology node through Cadence Virtuoso tool. ST9T SRAM cell shows a considerable improvement in read stability which is 2.8\(\times \) and 2.25\(\times \) higher in comparison to considered SRAM cells. ST 9T SRAM cell has the highest read stability as compared among the considered SRAM cells. The read/write power of the ST9T SRAM cell is 1.52\(\times \) and 1.47\(\times \)/3.12\(\times \) and 5.39\(\times \) lower as compared to conventional 6T and 8T SRAM cells, respectively. The process variation effects are also analyzed through Monte Carlo simulation under 5000 random samples. It has been found that the ST9T SRAM cell has the lowest variability among considered cells. Such improvements in the characteristics of ST9T SRAM make it suitable for ultra-low power applications. All the comparisons have been performed at 0.3V supply voltage.

The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challenges. To perform the comparative analysis, considered SRAM cell topologies are simulated with cadence virtuoso IC6.1.5-64b at 45 nm generic process design kit technology file. It is worthy to notice that 9T SRAM cell has highest value of read stability among considered cells. It is attributed to use of differential read decoupled structure. The 7T SRAM cell has highest value of write ability among considered cells. It is observed that 8T SRAM cell has lowest read power dissipation among considered cells. It happens due to the use of stack transistor in read path of the cell. The lowest value of read access time is also observed in 8T SRAM cell among considered SRAM cells. It is 1.82 $$\times$$ higher as compared to conventional 6T SRAM cell. Further, the write access time of 9T SRAM cell is lowest among considered cells. This is 1.41 $$\times$$ less as compared to conventional 6T SRAM cell. Static noise per unit area to power delay product ratio (SAPR) is used to evaluate the overall performance of considered SRAM topologies. It is observed that 8T SRAM cell has the highest value of SAPR among considered SRAM cells. It is 1.91 $$\times$$ as compared to conventional 6T SRAM cell. All the comparison has been done at 1.0 V supply voltage.

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

In ultra-Low power application the supply volt- age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.

Gated Clock as well as Gated power have demonstrated to be very operative elucidations for Lessing active as well as leakage power, respectively. These method applied in the same circuit that the gated clock or transmission gated circuit is used to reduce dynamic power dissipation. Our main concern is to analysis of power dissipation of 32 bit ROM by applying the gating technique. This paper integrates both the method of minimizing power dissipation. Lessening the leakage power dissipation, gated power technique is used. On the other hand reducing the dynamic power dissipation gated Clock with transmission gate enabled & latch free technique are use. Starting from gated clock technique with low voltage complementary metal oxide semiconductor (LVCMOS) input-output standard in Xilinx. After that gated clock and gated power technique both are implemented by help of Tanner EDA tool. There is significant reduction in static as well as dynamic power have been seen by help of Tanner EDA tool.

Fundamental memory has turned out to be one of largest contributors to overall energy consumption and offer many opportunities for power reduction. Power dissipation plays important role in portable products that can store, receive and transmit data because in each operation cycle the power is consumed by the operator. The goal of this paper is to use Frequency scaling approach in Random Access Memory to minimize power dissipation by the help of High Speed Transceiver Logic (HSTL) input output standard. These techniques cover RTL coding. This research suggest that there is 75% reduction clock power 66.66% reduction in Signal power, (35.20% to 47.77%) reduction in IOs power when the frequency are minimize. This design is implemented on Artex-7.