An ion-implanted $\text{Ga}_{2} \mathrm{O}_{3}$ substrate was bonded to a SiC substrate and annealed at $500{ }^{\circ} \mathrm{C}$. At this temperature, partial bonding between the $\text{Ga}_{2} \mathrm{O}_{3}$ and SiC surfaces occurred, and the $\text{Ga}_{2} \mathrm{O}_{3}$ layer was simultaneously split by ion cutting. This technique could contribute to the development of future power electronics that leverage the advantages of both $\text{Ga}_{2} \mathrm{O}_{3}$ and SiC.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have garnered significant attention owing to their exceptional performance in high-frequency and high-power applications. Despite these advantages, the self-heating of these HEMTs during high-power operation remains a major limitation. To overcome this, a 30-mm-square GaN-on-diamond high-electron-mobility transistor (GoD-HEMT) was successfully fabricated with a bonding ratio exceeding 95 % using a surface-activated bonding method with a Si layer. The GaN substrate was polished by chemical-mechanical polishing, while the diamond substrate underwent 172 nm vacuum ultraviolet-assisted polishing, resulting in a surface roughness (Sq) of <0.4 nm for both substrates. The GaN/diamond bonding interface exhibited an atomically bonded amorphous structure (similar to 4.5 nm thick) composed of C and Si layers. These results demonstrate that high-precision surface preparation and the formation of an amorphous interfacial structure enable the successful large-area bonding of GaN and diamond, despite their significantly different lattice constants.

A silicon-based vapor chamber incorporating jumping droplet structures was developed using MEMS technology. Superhydrophobic micropillar surfaces were fabricated to enhance working fluid circulation, enabling efficient heat spreading for compact electronic devices.

This study analyzes warpage in diamond/Si bonded wafers using an analytical model that incorporates thermal strain and vacuum chucking. The model predicts a substrate-size-dependent reduction in total thickness variation, and the results agree well with finite element simulations.

Because the coefficients of thermal expansion of diamond and Si intersect at around $600{ }^{\circ} \mathrm{C}$, thermal stress can be mitigated by increasing the bonding temperature above this point. Surface profiles were compared for diamond/Si wafers bonded at different temperatures. The height variation decreased from $27 \mu \mathrm{m}$ to $9 \mu \mathrm{m}$ as the bonding temperature increased from 1000 °C to 1200 °C. Achieving such flat diamond/Si wafers is expected to contribute to wafer-scale production of diamond electronics.

For the wafer-scale fabrication of diamond electronic devices, diamond/Si composite wafers were fabricated with low warpage using high-temperature bonding. Typically, thermal warpage increases with the bonding temperature because of the mismatch in the thermal expansion coefficients. However, in the diamond/Si system, thermal stress can be reduced at higher bonding temperatures because the coefficients of thermal expansion of diamond and Si reverse at approximately 600 degrees C. This study compares the warpage of diamond/Si wafers bonded at 1000 and 1200 degrees C. The height difference between the highest and lowest points of a vacuum-chucked wafer was 26 and 9 mu m, respectively. The reduced surface warpage enables precise patterning of 1 mu m-wide line-and-space structures using stepper lithgraphy, confirming the bonded wafer's compatibility with the micropatterning process. Additionally, high-temperature bonding formed a 5 nm-thick interfused layer containing Si-O, C-O, and Si-C bonding networks. This contributes to a high tensile bonding strength of 14 MPa, thermal tolerance up to 1000 degrees C annealing, and chemical durability against NH4OH, HCl, H2SO4, H2O2, and HF. These results demonstrate that diamond/Si composite wafers are promising platforms for wafer-scale diamond electronics, effectively overcoming the size limitations associated with homoepitaxially grown diamond substrates.

An accelerated impedance test was performed to evaluate gold wiring of a micrometer-scale line width for highdensity integration between parylene-C based neural electrodes and a readout chip. The impedance degraded, and we estimated the equivalent time to be $\boldsymbol{\sim} \mathbf{1 2 1}$ days using an Arrhenius model.

The fabrication of highly functional optical devices requires solid-state, low-pressure bonding techniques. In this study, we developed micro-bump Au arrays that come into close contact at low pressure and facilitate low-temperature bonding. The micro-bumps were fabricated by Au film transfer and coining methods. A high die shear strength was achieved between the Si chip with the micro-bumps and the Si substrate with an Au film under a low bonding pressure of 10 MPa in ambient air at 150 °C after Ar fast-atom beam irradiation. The close contact between the micro-bumps and Au film was confirmed via cross-sectional scanning electron microscopy. Using the micro-bumps, a GaAs laser diode chip with an active layer near the bonding interface was junction-down mounted without degradation. The study findings confirm that the proposed methods can bond dissimilar materials at low bonding pressures, thereby contributing to the integration of optical components.

Room temperature bonding of Au plating offers various applications in electronics packaging, but smoothing of the bonding surface is a critical challenge. In this study, we propose and demonstrate the additive smoothing of the plated Au surface by combining the template stripping and surface activated bonding techniques for direct Au bonding at room temperature. The surface roughness of the Au plating is reduced from 21 nm to 5 nm in RMS by transferring Au films from the polyimide (PI) template three times. It is found that the transferred Au films from the PI template compensate the surface asperity of the Au plating, resulting in fewer gaps at the interface than using a SiO2 template. The smoothed Au plating is also bonded through surface activated bonding at room temperature, exhibiting as high bonding strength as bulk fracture. The presented method enables room temperature bonding of plated Au without conventional polishing processes.

Under ultrahigh vacuum conditions, beta-Ga2O3 and Si surfaces form atomic bonds after surface sputtering treatment. It enables the formation of a beta-Ga2O3/Si heterostructure, which can contribute to future high-power devices integrated with conventional systems. However, the surface sputtering step generates crystalline damage, hindering electrical conductance across materials. In this study, sputtering conditions were optimized to maximize electrical conductance, and the effects of annealing were investigated to initiate recrystallization. The current between substrates was maximized when Si was sputtered for 40 s and beta-Ga2O3 was not sputtered. In addition, annealing at 500 degrees C achieved ohmic-like current-voltage characteristics between n-type beta-Ga2O3 and n-type Si substrates because of recrystallization. An electrically conductive interface can contribute to heterodevices combining beta-Ga2O3 devices, which have difficulty in p-type doping, with other materials. (c) 2025 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license

The manufacture of diamond devices requires a micropatterning process on diamond substrates. Although conventional patterning processes involving photolithography are complex, this study demonstrates that Ni molds designed for nanoimprint lithography can be used to fabricate micropatterns on diamond surfaces through a solid solution reaction. The dissolved carbon atoms precipitate as graphite at the Ni/diamond interface. This study shows that an additional annealing process causes thermal stress between Ni and diamond, resulting in the exfoliation of the patterned diamond substrate from the Ni mold. This etching process fabricates line and space patterns measuring 5 mu m in width and 2 mu m in depth on the diamond surface. Furthermore, after cleaning the exfoliated Ni mold, diamond micropatterns could be fabricated again. This facile patterning method, involving stamping the Ni mold, is promising for the fabrication of diamond microdevices.

Low-temperature, low-pressure bonding is crucial for fabricating highly functional microsystems. This study presents the development of Au hollow pyramidal bumps (height: 4 mu m, width: 6 mu m, pitch: 12 mu m) that plastically deform under low bonding pressure and facilitate low-temperature Au-Au bonding. The bump arrays were fabricated using the Au film transfer method. A strong bond reaching the fracture strength of bulk Si was formed between the Si chip with Au hollow pyramidal bumps and the Si substrate with Au film at 150 degrees C in ambient air. Furthermore, finite element method simulations reveal that hollow pyramidal bumps reduce stress concentration on the devices during bonding. The study findings confirm that the proposed method enables bonding of device chips at low temperatures with reduced stress concentrations, thereby contributing to the fabrication of microsystems.

For low-temperature solid-state Au-Au bonding, the bonding surfaces must be smooth. In this study, we used a multiple Au thin-film transfer method based on template stripping to obtain smooth Au surfaces for low-temperature bonding. We employed and compared polyimide films and thermally oxidized Si substrates as template substrates. By transferring the Au thin film from the PI template to the surfaces of the rough-plated Au bumps, the RMS surface roughness decreased from 30 nm to 6 nm with an area of 10x10 µm2, enabling bonding at room temperature.

Although Germanium devices have attracted attention for post-silicon device applications, they suffer from heat dissipation problems that hinder miniaturization. This study demonstrates the low-temperature and vacuum-free bonding of a germanium substrate with a diamond heat spreader, which has the highest thermal conductivity among solid materials. For efficient heat dissipation, we designed a bonding process at 200°C using a reduction pre-bonding treatment instead of conventional oxidation. The process suppresses the formation of a germanium oxide layer at the bonding interface. This study demonstrates that germanium and diamond substrates are bonded through a 1.6-nm-thick amorphous intermediate layer. The shear stress reached 9.43 MPa, satisfying the MIL-STD-883E standard for microelectronics. As the germanium substrate can form atomic bonds with thermally conductive materials through a thin interfacial layer, it is expected that the bonding process of the HCl-dipped Ge device can contribute to future high-frequency devices.

Bonding formation is possibly affected by crystal orientations, which are deeply related to surface reaction. This study compared the crystal orientation dependence on the bonding strength using Ge and diamond substrates. The bonding of the Ge (100) and (111) surfaces is similar; however, that of diamond (100) and (111) surfaces significantly differs. Understanding the relationship between crystal orientation and bonding formation can contribute to the design of next-generation semiconductors.

150μm thick GaN-on-Diamond high electron mobility transistors have been successfully fabricated by surface-activated room-temperature bonding. Surfaces of the both GaN-HEMTs and the 150μm thick diamond substrate are polished and bonded each other with a thin Si interlayer by surface-activated room-temperature bonding. Fabricated devices have demonstrated higher drain current at high drain voltage region in comparison with devices with a conventional structure.

A 20-mm-square diamond substrate was bonded with a 2-inch-diameter GaN wafer by hydrophilic bonding method. Both substrates were cleaned with an NH 4 OH/H 2 O 2 mixture and then bonded at 200 °C under atmospheric conditions. The diamond substrate planarized by plasma-assisted polishing was bonded without visible voids. As this simple process enables relatively large-scale GaN/diamond bonding, it would contribute to future GaN-on-diamond devices.

Surface roughness is a dominant factor for low-temperature Au-Au solid-state bonding. Here, we present a multiple Au thin-film transfer method using a template-stripping method for obtaining smooth Au surfaces to achieve bonding at low temperatures. Polyimide films and Si substrates with thermal oxide (SiO 2 ) films were used as templates. By transferring Au thin films from the templates to the rough plated Au surfaces, rms surface roughness of rough plated Au surfaces decreased from 21 nm to sub-nanometers (scan area: 10 × 10 µm 2 ). Using Si chips with templated-stripped Au thin films, room-temperature Au-Au bonding was realized in air atmosphere environment.

The present study compares the electrical properties of n-Ga 2 O 3 /n-Si substrates bonded under different conditions. The results indicate that the Ar fast-atom beam irradiation for the Ga 2 O 3 surface deteriorates the electrical conductance at the Ga 2 O 3 /Si bonding interface.

Au flat micro-bump arrays that facilitate low-pressure Au-Au bonding were fabricated by the process based on Au thin film transfer and coining of Au hollow structure. High die shear strength was achieved between Au flat bumps and Au sputter films with a low bonding pressure of 10 MPa at 150°C.