A wet-etching technique based on a mixture of hydrochloric (HCl) and nitric (HNO3) acids is introduced, demonstrating exceptional 42:1 selectivity for etching N-polar GaN over Al0.24Ga0.76N. In the absence of an AlGaN etch stop layer, the etchant primarily targets N-polar unintentionally doped (UID) GaN, indicating its potential as a suitable replacement for selective dry etches in the fabrication of GaN high-electron-mobility transistors (HEMTs). The efficacy and selectivity of this etchant were confirmed through its application to a gate recess module of a deep-recess HEMT, where, despite a 228% over-etch, the 2.6 nm AlGaN etch stop layer remained intact. We also evaluated the proposed method for the selective etching of the GaN cap in the n+ regrowth process, achieving a contact resistance matching that of a BCl3/SF6 ICP process. These findings underscore the applicability and versatility of the etchant in both the electronic and photonic domains and are particularly applicable to the development of N-polar deep-recess HEMTs.

Tunneling FET (TFET) has been demonstrated as a favorable candidate to replace conventional MOSFETs in low-power applications. However, there are many challenges that should be overcome to efficiently operate the TFET. One of the most limiting factors that can restrict the TFET performance is the gate leakage current. In this paper, the tunneling leakage current through the gate oxide of double gate TFET has been analyzed. The conduction band energy level for gate-oxide-silicon was employed to calculate the tunneling transmission coefficient by utilizing a numerical method. To obtain the potential barrier between the gate and the channel surface, a modified analytical pseudo-2D method has been applied to deduce the corresponding surface potential taking into account a precise calculation of depletion regions. Furthermore, the inclusion of the image charge barrier lowering effect is incorporated in calculating the transmission probability through the oxide. Including such an effect shows a significant influence on determining the gate tunneling current. The gate leakage current has been calculated for various bias voltages and equivalent oxide thicknesses. The presented semi-numerical technique shows good agreement within a suitable CPU time when validated and compared against full numerical TCAD simulation.

TFET accurate physically based models are highly required to analyze and predict the device characteristics for its future utilization in circuits. In order to precisely model TFETs, it is essential to understand the several aspects related to the physics-based modeling of these devices. Using 2D TCAD simulation, we showed that in order to appropriately model the electrostatic potential in InAs-based TFETs, the electron quasi-Fermi potential (eQFP) should be taken to depend on biasing conditions, both VDS and VGS, contrary to the case of Si-based TFETs in which the eQFP is considered independent of VGS which is widely encountered in the literature. The study is carried out for InAs double-gate homojunction tunnel FETs (DG-TFETs). In addition, we applied the main key factor of dependence of eQFP on a modified TFET model and it is revealed that the interpretation of eQFP correctly predicts the electrostatic potential and the drain-to-source band to band tunneling current.

Achieving high-quality, relaxed InGaN substrates for longer-wavelength light emitting diodes (LEDs) is of great interest for the development of micro-LED based display technology. This work demonstrates molecular beam epitaxy (MBE)-grown In0.2Ga0.8N with a strain relaxation of 60% corresponding to an equivalently fully relaxed In composition of 12%. This was done by growing on a GaN-on-porous GaN pseudo-substrate (PS). The surface morphology of this film was found to be free of V-defects on the surface and with a threading dislocation density comparable to that of the GaN layers beneath. While InGaN grown on planar GaN-on-sapphire substrates remained nearly strained to the GaN underlayer, InGaN grown under identical conditions on PS displayed elastic-like relaxation. Furthermore, an increase in indium (In) composition was observed for the InGaN grown on PS. Where past work of InGaN grown on porous GaN PS by metalorganic chemical vapor deposition also resulted in relaxed InGaN templates suitable for device application, the surfaces of these relaxed films exhibited V-defects for thicker layers. Employing MBE, thicker films with higher In composition can be achieved with smooth surface morphology, thus enabling pseudo-substrates with a wide range of lattice constants. These pseudo-substrates of varying in-plane lattice constant are attractive for III-nitride based optoelectronics, particularly for green, amber, and red micro-LEDs.

Device-quality, relaxed InGaN substrates has been a topic of great interest, particularly for longer wavelength optoelectronics. This work demonstrates MBE-grown In0.2Ga0.8N with a strain relaxation of 60% corresponding to an equivalently fully relaxed In-composition of 12% achieved by growing on a GaN-on-porous GaN pseudo-substrate (PS). The surface morphology of this film was found to be free of V-defects on the surface and with a threading dislocation density comparable to that of the GaN layers beneath.

UV-assisted capacitance–voltage (C–V) and current–voltage (I–V) measurements were performed on ∼20 nm HfO2/GaN metal–insulator–semiconductor capacitors. The effects of surface preparation, predeposition treatment, HfO2 deposition process, and post-deposition annealing environment on interface characteristics were studied. Surface preparation by etching in diluted BHF and piranha etch prior to atomic layer deposition (ALD) suppressed the interface states compared to the baseline sample possibly due to the removal of the native oxide and impurities. UV/ozone treatment prior to HfO2 deposition reduced the interface states by one order of magnitude compared to the baseline sample possibly due to the formation of a thin Ga2O3 interlayer. In situ ALD pretreatment with tri-methyl-aluminum/N2 plasma was also found to reduce the surface states significantly compared to the baseline sample. In addition, thermal ALD improved the dielectric constant and breakdown voltage of the dielectric as compared to plasma ALD due to less surface damage. The lowest average interface trap density achieved was 1.64 × 1012 cm−2/eV with an HfO2 dielectric constant of 16 on the sample with UV/ozone and piranha treatment with in situ ALD treatment and thermal ALD deposition.

In this work, we studied the impact of post-metallization annealing (PMA) on interfacial and bulk dielectric properties of AlSiO/beta-Ga2O3 metal-oxide-semiconductor capacitors (MOSCAPs). Annealing at 300 degrees C improved the reverse operational stability within the test operation range from -10 V to -42 V. The near-interface fast and slow traps were both suppressed by PMA at 300 degrees C and 350 degrees C, leading to a negligible flat-band voltage hysteresis. The low gate leakage region was extended from 3.7 MV cm(-1) to 4 MV cm(-1) and the breakdown strength was improved from 7.8 MV cm(-1) to 8.2 MV cm(-1) for AlSiO/beta-Ga2O3 MOSCAPs with PMA at 300 degrees C compared with not-annealed samples. The superior operational reliability demonstrated in this work is useful for future high-performance and reliable MOS-based Ga2O3 transistors.

This work investigates the process of planar electrochemical etching of pores in n-type nitrogen-polar GaN and the effect of pore morphology on regrown GaN film surface quality. An increase in the anodization voltage was found to increase the pore diameter and reduce the density of pores with inclined sidewalls near the surface of the porosified films. Simultaneously, a decrease in the hexagonal hillock size and number following GaN regrowth was observed. It is proposed that vertical pore sidewalls are essential to demonstrate high quality film coalescence. For smooth hillock-free 100 nm GaN regrowth, an optimal bias of 17 and 13 V for Ti-contacted N-polar GaN:Si with a Si doping of 4.5 × 1018 and 8 × 1018 cm−3, respectively, was found.

The interface and bulk properties of aluminum-silicon-oxide (AlSiO) dielectric grown by metal-organic chemical vapor deposition (MOCVD) on (001) β-Ga2O3 were investigated systematically using a deep UV-assisted capacitance–voltage methodology. The improved surface preparation with a combination of UV-ozone and wet chemical treatment reduced near-interface traps resulting in a negligible hysteresis. An average interface state density of 6.63 × 1011 cm−2 eV−1 and AlSiO bulk trap density of 4.65 × 1017 cm−3 eV−1 were quantified, which is half of that for Al2O3 deposited by atomic layer deposition (ALD). A net positive interface fixed charge of 1.56 × 1012 cm−2 was measured. In addition, a high dielectric breakdown field of ∼7.8 MV/cm and more effective suppression of gate leakage were achieved on these devices compared with ALD-Al2O3 on similar metal-oxide-semiconductor (MOS) structures.

GaN-based transistors offers the highest power density for radio-frequency (RF) applications. However, self-heating significantly limits device performance and reliability that must be managed for the transistors to perform. Exploiting the high thermal conductivity of polycrystalline diamond (300-2000 Wm -1 K -1 near room temperature), we have demonstrated polycrystalline diamond integration on top of the GaN channels for effective device cooling, while preserving its electrical performance. Various thicknesses of polycrystalline diamond were grown on top of the GaN channel to investigate its impact on the device temperature. Using Raman thermometry, a remarkably lower temperature (by 30-60 °C) was measured in the channel for devices with diamond compared to control devices without diamond. The effect of diamond thickness (250-650 nm) and device layout on the heat dissipation was carefully studied and discussed. We have shown that thicker diamond (~650 nm) along with the metal-diamond overlap improves channel cooling capabilities of the diamond heat spreader by a factor of two.

We propose the existence of an acceptor-like trap at positive polarization interfaces in p-type III-nitride semiconductor heterostructures, using N-polar p-type GaN/AlN/AlGaN superlattices as a demonstration platform. Metal Organic Vapor Phase Epitaxy was used to grow all samples, with a p-type modulation doping scheme using Mg as the dopant. The samples were characterized using x-ray diffraction and room-temperature Hall measurements, and energy band-diagram simulations were carried out using STR FETIS® and Silvaco packages. For higher doped samples (Mg > 1.5 × 1019 cm−3) with thinner AlN interlayers (≤0.7 nm), the total sheet charge measured using Hall measurements agreed with the value observed in standard simulations without invoking any traps, whereas for lower doped samples (Mg < 1.5 × 1019 cm−3) and those with thicker AlN interlayers (≥ 0.7 nm), the measured charge was very high compared to the value obtained from simulations and higher than the Mg doping in the films. The higher charge was attributed to the existence of an acceptor trap at positive polarization interfaces, which became ionized at lower doping and/or at higher AlN thicknesses. A consistent ionization energy of the trap was obtained by comparing the energy band diagram with and without acceptor traps with the experimental results. This work also elucidates the source of charge balance in p-type samples with insufficient or no Mg doping.

In this Letter, a series of metal-insulator-semiconductor capacitors consisting of Si3N4 dielectrics with different thicknesses on GaN have been fabricated to investigate their interface states. The measurement value extracted from ultraviolet assisted capacitance-voltage methods can be explained by the existence of spatially uniform hole traps in Si3N4. An improved model combining the effects from interface states and hole traps in Si3N4 is proposed to extract the interface state density (Dit) accurately. Based on the model, Dit can be obtained by extrapolating the trap density to a zero-thickness dielectric. The extracted average Dit value of the Si3N4/GaN interface is ∼3.8 × 1011 cm−2 eV−1, and the hole trap concentration in Si3N4 is ∼3.1 × 1018 cm−3. The results, model, and analysis presented here provide new insights into studying Dit of various dielectrics on GaN and other wide-bandgap semiconductors.

The properties of aluminum-silicon-oxide (AlSiO) dielectric with varying silicon composition, grown on (000-1) N-polar GaN, were investigated in this paper. The refractive index, dielectric constant, and film density of AlSiO decreased with the increase of the silicon composition as indicated by ellipsometry, low-frequency capacitance-voltage (CV), and x-ray reflectivity (XRR) measurements, respectively. Negligible frequency dispersion in CV measurements and high-intensity XRR oscillations peaks were measured for all AlSiO samples with different silicon compositions, suggesting a high-quality N-polar GaN-AlSiO interface. The leakage current characteristics and flat-band voltage stability improved with the increase of the silicon composition from 20% to 46% and degraded for the sample that had a silicon composition of 73%. This study contributes to understanding the AlSiO dielectric performance for future use in the gate stack of N-polar GaN-based transistors.

The bulk and interfacial properties of aluminum silicon oxide (AlSiO) on N-polar GaN were investigated systematically employing capacitance–voltage (C–V) methods on metal–oxide–semiconductor capacitors using a thickness series of the AlSiO dielectric. The fixed charge density, electron slow trap density, and electron fast trap density located near the interface were extracted to be –1.5 × 1012 cm−2, 3.7 × 1011 cm−2, and 1.9 × 1011 cm−2, respectively. Using ultraviolet (UV) assisted C–V methods, an average interface state density of ∼4.4 × 1011 cm−2 eV−1 and a hole trap concentration in bulk AlSiO of ∼8.4 × 1018 cm−3 were measured. The negative fixed interface charge makes it favorable to achieve a normally off GaN transistor. The analysis presented in this paper provides a systematic and quantitative model to study the properties of oxide dielectrics on wide bandgap (WBG) semiconductors, which can promote the development of metal–oxide–semiconductor-based WBG semiconductor devices.

We present a novel, low temperature approach to multijunction solar cell fabrication combining the high efficiency multi-junction concept with the low cost of thin film technology in one solar cell structure. The intermetallic bonding approach presented is based on joining indium metal which has been deposited on the metal contact grid of the respective solar cells. This approach avoids the problems of lattice mismatch and tunnel junction limitations, connecting solar cells of potentially any material with patterned contacts. No measurable increase in resistance has been measured between bonded materials. This method allows the independent development of each cell technology for use in multijunction solar cells. This technique can be applied to any commercial off-the-shelf solar cells, if available. A GaAs/Si multijunction solar cell bonded using this approach is demonstrated. The silicon cell is off-the-shelf with textured surface and commercial metal contacts. This is integrated with an in-house grown thin film GaAs cell. The GaAs/Si device is demonstrated in both two and three terminal configurations.

N-polar GaN based HEMTs have demonstrated superior performance for solid-state millimeter wave power amplifiers [1] , [2] . To further improve the high-frequency and high-power performance in N-polar GaN HEMTs, using a small gate length while preserving a good aspect ratio is critical. Currently, N-polar HEMTs utilize a thin gate dielectric to reduce gate leakage. This reduces the aspect ratio. Therefore, removing the gate dielectrics, i.e. using Schottky-HEMTs in N-polar GaN is very attractive to pursue highly scaled and high-performance devices. Previous studies [3] – [6] have shown that the barrier heights between the gate metals and N-polar GaN are relatively low and the reverse leakages may be too high to be used in practical Schottky-HEMTs. Here, we report the first investigation of ruthenium (Ru) on N-polar GaN Schottky barrier. The device shows near-ideal Schottky characteristic under reverse bias and forward bias . The barrier height values at various temperatures extracted from the forward bias region and the reverse bias region agree well. The extracted barrier height is 0.77 eV at room temperature. The reverse leakage is ultralow with ~10 -6 A/cm 2 at -5 V and follows ideal thermionic behavior .

The impact of post-metallization annealing of N-polar AlSiO metal-oxide semiconductor (MOS) capacitors was investigated. Annealing in air at 320 degrees C and 370 degrees C reduced the density of near-interface traps from 5.6 x 10(11) to similar to 2.8 x 10(11) cm(-2) and extended the region of flat-band voltage stability and low-leakage operation from 0-2.6 to 0-4 MV cm(-1) in the forward bias accumulation region. Moreover, annealing at 370 degrees C fully suppressed the instabilities in the flat-band voltage within the test voltage range (-10 to -25 V) of depletion operation. The robust dielectric results demonstrated in this letter are promising for further enhancements of gate-robustness in N-polar GaN-based MOS-based transistors.

In this letter, we report the Schottky barrier diode investigation of ruthenium (Ru) deposited by atomic layer deposition on N-polar GaN. The Schottky diodes showed near-ideal thermionic current behavior under forward bias and reverse bias at various temperatures. The barrier height values extracted from both regions agreed well at each temperature and the barrier was extracted to be 0.77 eV at room temperature. The combination of the 0.77 eV barrier and thermionic current characteristic resulted in <2 mu A/cm(2) reverse current at -5 V, which is a record-low value for N-polar GaN Schottky diodes. As a comparison, theRu onGa-polarGaN Schottky barrier diode, which has a barrier height of 1.0 eV, exhibited a similar to two-order ofmagnitude higher leakage than Ru on N-polarGaN at -5V due to other parasitic leakage mechanisms.

The electrical properties and trapping characteristics of Si3N4 and SiO2 dielectrics grown in situ on (000-1) N-polar GaN by metal organic chemical vapor deposition are investigated in this paper. The fixed charges, densities of near-interface trap states, and interface trap density in N-polar Si3N4 and SiO2 metal insulator semiconductor capacitors (MISCAPs) are quantified using a capacitance-voltage measurement method which is assisted by ultraviolet illumination and applied voltage-stress. The fixed charges and trap states are located at or near the interface of Si3N4 (SiO2)/N-polar GaN as indicated by the linear relationship between the flatband voltage/hysteresis and the Si3N4 (SiO2) thickness. Positive flatband voltages were measured for both the N-polar Si3N4 and SiO2 MISCAPs which is a promising route toward realizing normally off GaN-based metal insulator semiconductor power devices. Net negative fixed charge densities of 2.9 × 1012 cm−2 and 3.3 × 1012 cm−2 are located at the interface of Si3N4/GaN (N-polar) and SiO2/GaN (N-polar), respectively. The origin of this net negative interface fixed charge is briefly discussed, and the trap densities with fast and slow emission rates are quantified in both the N-polar Si3N4 and SiO2 MISCAPs. This study is a step toward identifying suitable gate dielectrics that can be integrated into N-polar high electron mobility transistors for high-frequency and switching applications.

We present a low temperature and low pressure approach to multijunction solar cell fabrication combining the high efficiency multi-junction concept with the low cost of thin film technology in one solar cell structure. The intermetallic bonding approach presented bonds indium metal covering metal contacts of the respective solar cells. This approach avoids lattice mismatch and tunnel junction limitations in connecting solar cells of any material and permits bonding of commercial off the shelf devices or textured surfaces. A two or three terminal GaAs/Si multijunction solar cell bonded using this approach is demonstrated using an off the shelf Si solar cell.