A 24%‐efficient single‐junction GaAs solar cell grown directly on a faceted, spalled (100) GaAs substrate after in situ planarization growth by hydride vapor phase epitaxy (HVPE) is achieved. Controlled spalling, a promising low‐cost substrate reuse technique, produces large facets in (100)‐oriented GaAs substrates due to the orientation of the fracture planes used for lift‐off. Planarization by HVPE offers a path toward direct use of these spalled substrates without costly polishing steps. Here, the growth rate anisotropy enabling planarization arising from diffusion and differences in the adsorption of growth species on {n11}B‐type facets relative to (100) is determined. Consecutive planarization and device growth that results in a solar cell with a minimal performance difference relative to a control cell grown on an epitaxy‐ready substrate are demonstrated. These results show that controlled spalling coupled with HVPE planarization is a viable pathway for lowering the cost of III‐V photovoltaics.

We report on the development of GaAs solar cells directly grown on nanopatterned V-groove Si substrates by metalorganic vapor-phase epitaxy (MOVPE). A low threading dislocation density (TDD) of 3×106 cm-2 was achieved in the GaAs through a combination of thermal cycle annealing and InGaAs dislocation filter layers. Front junction GaAs solar cells were then grown on these low-TDD substrates, but preliminary devices produced a conversion efficiency of only 6.6% without an anti-reflection coating. Electron channeling constast imaging measurements on this cell showed a high density of misfit dislocations at the interface between the AlInP/GaInP window layer and GaAs absorber, likely causing poor surface passivation and thus poor performance. The source of these misfit dislocations will be discussed, as well as mitigation strategies to improve solar cell performance.

To date, the greatest performance limiter in monolithic III-V/Si tandem (multijunction) solar cells, like GaAs 0.75 P 0.25 /Si, is excess threading dislocation densities (TDD) resulting from the lattice-mismatched heteroepitaxy. Recent developments in low-TDD GaAs (y) P (1-) (y) /Si metamorphic buffers were used to grow standalone GaAs 0.75 P 0.25 top cells on Si with a TDD of 4 x 10 (6) cm (-2) , similar to 2.5 x lower than previous iterations, greatly improving the potential for the production of high-efficiency tandems based on this platform. Nonetheless, these reduced-TDD cells were still found to possess considerable voltage-dependent carrier collection (VDC) losses. As such, to improve J (SC) and fill factor, without sacrificial reduction in V (OC) , a doping gradient within the cell base layer was designed and implemented. The updated design reduces VDC losses to levels that would otherwise require further TDD reduction by at least another 2.5 x (to <= 1.5 x 10 (6) cm (-2) ) in a typical flat doping profile design. Replacing the p (+) -Ga 0.64 In 0.36 P back surface field with p (+) -Al 0.2 Ga 0.8 As 0.74 P 0.26 provided an additional improvement in both V (OC) and J (SC) , yielding device performance equivalent to a 4 x TDD reduction in the previous design. The culmination of these design changes results in a new subcell that outperforms our previous best top cell by similar to 4.3% absolute AM1.5G efficiency, with increases in fill factor, J (SC) , and W (OC) of about 3.3% absolute, 1.9 mA/cm (2) , and 0.12 V, respectively. This new design, coupled with the reduced TDD platform, paves a promising path toward the development of higher efficiency GaAs 0.75 P 0.25 /Si tandems upon full device integration.

One possible pathway toward reducing the cost of III-V solar cells is to remove them from their growth substrate by spalling fracture, and then reuse the substrate for the growth of multiple cells. Here we consider the growth of III-V cells on spalled GaAs(100) substrates, which typically have faceted surfaces after spalling. To facilitate the growth of high-quality cells, these faceted surfaces should be smoothed prior to cell growth. In this study, we show that these surfaces can be smoothed during organometallic vapor-phase epitaxy growth, but the choice of epilayer material and modification of the various surfaces by impurities/dopants greatly impacts whether or not the surface becomes smooth, and how rapidly the smoothing occurs. Representative examples are presented along with a discussion of the underlying growth processes. Although this work was motivated by solar cell growth, the methods are generally applicable to the growth of any III-V device on a nonplanar substrate.

We analyze the effect of surface morphology created by planarizing spalled GaAs wafers on GaAs solar cells grown by HVPE. Controlled spalling of (100)-oriented GaAs has potential to reduce substrate costs for III-V photovoltaics (PV); however, it creates regularly faceted surfaces that complicate the growth of high quality III-V PV devices. We leverage the crystallographic-direction-dependent growth capability of hydride vapor phase epitaxy (HVPE) to planarize these faceted GaAs substrates, reducing the surface roughness and degree of faceting. We then demonstrate that GaAs solar cells grown on planarized surfaces are nominally identical to those grown on a planar, epi-ready GaAs surface. We observe slightly degraded device performance in cases where facets are not completely removed. We use device-scale imaging techniques combined with characterization of device cross sections to analyze this performance degradation. Lastly, we discuss the growth mechanisms that contribute to the planarization of faceted surfaces. These investigations into the mechanisms of both device degradation and planarizing growth will ultimately enable high-performing III- V PV with the cost reduction potential of controlled spalling. This advancement, when combined with low-cost epitaxy by HVPE, provides one of the most promising routes to low-cost III- V PV to date.

We analyze the effect of growth on non-(100) surfaces resulting from incomplete planarization of spalled GaAs wafers on the defect structure of GaAs solar cell layers grown by hydride vapor phase epitaxy (HVPE). Controlled spalling of (100)-oriented GaAs has the potential to reduce substrate costs for III-V epitaxy; however, it creates regularly faceted surfaces that may complicate the growth of high-quality III-V optoelectronic devices. We leverage the anisotropic growth rate of HVPE to planarize these faceted GaAs substrates, reducing the surface roughness and degree of faceting. We observe degraded solar cell performance and material quality in sample areas where facets are not completely removed. We used dark lock-in thermography and photoluminescence to identify recombination in areas that were not fully planarized. We used cathodoluminescence to identify the presence of extended defects in these regions, which are correlated with bandgap fluctuations in the material. We hypothesize that these defects were created by strain from compositional fluctuations in ternary alloys grown on the faceted surfaces. This work elucidates the potential issues of solar cells grown on faceted surfaces and builds understanding toward realizing high performance III-V photovoltaics with the cost-reduction potential of controlled spalling.

We report the development of AlInP-passivated solar cells grown by dynamic hydride vapor-phase epitaxy (D-HVPE) with AM1.5G efficiencies of 26.0% for single-junction (1J) GaAs cells and 28.0% for GaInP/GaAs (2J) tandems. We compare the device performance of solar cells passivated with AlInP versus control cells passivated with GaInP, which has already enabled near-unity carrier collection in GaAs solar cells. 1J devices passivated with either AlInP or GaInP have an identical open-circuit voltage (V-OC) of 1.06 V and long-wavelength current collection near 95%, indicating that both window materials provide a similar degree of passivation. Adding AlInP passivation to each solar cell structure improves the current collection by 1.3 and 1 mA/cm(2) for the 1J and 2J, respectively. The AlInP also results in a top cell V-OC boost of similar to 40 mV relative to a tandem device passivated only by a thin, highly doped GaInP emitter. Secondary-ion mass spectrometry measurements indicate that although O and Si both incorporate in the AlInP window, they do not appear in the subsequently grown absorber layers and do not impact its ability to passivate the front surface. We expect that these achievements, along with continued optimization, will enable parity of hydride vapor-phase epitaxy (HVPE)-grown device efficiencies with state-of-the-art devices grown by other epitaxial methods in the near future.

We report the growth of high-efficiency GaAs solar cells grown by organometallic vapor phase epitaxy on non-flat substrate surfaces created by acoustic spalling, or “Sonic Lift-off” (SLO). SLO is a potentially low-cost source of III-V epitaxial growth substrates, but surface facets formed during the SLO process can impact the performance of subsequently-grown devices. We show that non-linear shunts can form in regions where the surface contains facets with 2-3 μm peak-to-valley height. These defects degrade the device performance via a reduction in open-circuit voltage, despite quantum efficiency measurements that suggest that the bulk material quality is only slightly affected by the surface roughness. We present evidence from electrical device measurements and structural analyses that these shunts form at regions of non-conformal coating of the epitaxial layers over surface features, which we hypothesize leads to the formation of Schottky diodes where the front contact grid-lines contact the p-type base of the n-on-p diode structure. We demonstrate that these defects can be mitigated or eliminated by planarizing the surface using wet chemical etching and/or growth. Using a combination of etching and growth planarization, we demonstrate 0.25 cm2 devices with 26.94% photovoltaic conversion efficiency under the one-sun AM1.5G spectrum grown on an acoustically spalled substrate. These results show that the growth of high performance III-V devices is possible on rougher, non-traditional substrates that offer the potential for reduced cost.

We present the first AlInP-passivated solar cells grown by dynamic hydride vapor phase epitaxy (D-HVPE). D-HVPE has potential to reduce the costs of III-V solar cell production, but historical challenges with the growth of high-quality Al-containing compounds placed a ceiling on photoconversion efficiencies of D-HVPE-grown solar cells. Our single junction (1J) GaAs and GaInP/GaAs (2J) tandems with AlInP passivation achieve AM1.5G efficiencies of 26.0% and 28.5%, respectively, which are the highest reported efficiencies for HVPE-grown devices of each type. 1J devices passivated with either AlInP or GaInP have an open circuit voltage of 1.06 V and similar long wavelength current collection, indicating that both windows provide a similar degree of passivation. Adding AlInP passivation to the 2J solar cell improves the VOC by ~50 mV relative to the device passivated by a GaInP emitter. AlInP windows enable short circuit current densities of >29 mA/cm2 and >14 mA/cm2 for the 1J cell and 2J GaInP top cell, respectively. These achievements remove one of the last barriers limiting parity of HVPE device efficiencies with state-of-the-art.

A high-performance metamorphic Al 0.2 Ga 0.8 As 0.75 P 0.25 /GaAs 0.75 P 0.25 heterojunction tunnel junction structure was developed for application to monolithic epitaxial GaAs 0.75 P 0.25 /Si 1.7 eV/1.1 eV bandgap tandem solar cells produced via metal-organic chemical vapor deposition. Doping optimization focused on both bulk doping concentrations and mitigating the transient incorporation effects that otherwise causes nonabrupt doping profiles in the Te doped layer. These efforts resulted in a fully relaxed metamorphic tunnel diode at the target lattice constant having a peak tunneling current density (JP) of 279.1 A·cm -2 and a zero-bias resistance-area product (RA) of 3.0 × 10 -4 Ω·cm 2 . After postgrowth annealing to emulate the thermal load of the GaAs 0.75 P 0.25 top cell growth and elimination of the performance-enhancing carbon activation anneal, the device achieved JP = 13.1 A·cm -2 and RA = 1.5 × 10 -3 Ω·cm 2 . These worst-case values are very promising as they enable the operation of GaAs 0.75 P 0.25 /Si tandems under one-sun AM1.5G illumination with negligible series resistance and at AM1.5D concentrations up to 240 suns with only 0.1% absolute efficiency loss.

In this work we present solar cells grown via hydride vapor phase epitaxy (HVPE) in NREL’s dynamic HVPE reactor. We show single junction GaAs and GaInP solar cells with efficiencies as high as 25.5% and 15.2% respectively, and dual junction solar cells with an efficiency of 24.9%.

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Historically, the performance of monolithically-integrated GaAsP/Si tandem solar cells has been limited by the presence of elevated TDD in the GaAsP subcell. However, our recent development of low-TDD GaAsP/Si virtual substrates has greatly improved the near-term potential for achieving high efficiency devices. In this work, development efforts employing this new low-TDD platform will be presented. First, our current certified record GaAsP/Si tandem cell (23.4% AM1.5G) is briefly analyzed, identifying the root cause of critical fill factor losses, which in turn informs subsequent design and optimization efforts. Second, the experimental development of high performance GaAsP subcells is shown, following device design strategies that improve J SC and fill factor without sacrificing V OC . Finally, conversion efficiency projections demonstrate that the achieved top cell performance metrics, combined with those expected from the newest bottom cell iteration, should enable ~27% efficient tandems.

To identify the complex relationships between early-stage growth processes and the resultant defect microstructure in GaP/Si heteroepitaxy, a holistic study of several key metal-organic chemical vapor deposition (MOCVD) parameters was conducted, focusing on Si surface preparation and GaP atomic layer epitaxy (ALE) based nucleation processes. Crystalline defects related to the lattice mismatch and/or interfacial heterovalency, namely misfit dislocations (MD), threading dislocations (TD), and stacking fault pyramids (SFP), were quantitatively characterized via electron channeling contrast imaging (ECCI) and correlated against the different process variations. Choice of Si surface preparation method between the two examined (dilute SiH4 annealing versus Si2H6 based homoepitaxy) had little impact on resultant GaP film morphology and defect content, whereas differing GaP ALE nucleation conditions produced much more substantial changes. In particular, the initial precursor species (tert-butylphosphine versus triethygallium) and ALE cycle purge times both yielded significant influence over threading dislocation densities (TDD) in thin (100 nm), post-critical thickness GaP/Si films, with TDD spanning two orders of magnitude, from 6.7 x 10(7) cm(-2) to 7.1 x 10(5) cm(-2), depending on the specific process conditions employed. SFP densities were also found to follow a similar trend, ranging from 2.0 x 10(7) cm(-2) to 1.8 x 10(5) cm(-2), but with no apparent causal relationship between SFP density and TDD. To help explain the dramatic differences observed, detailed, large-area MD network characterization was used to provide statistically-relevant quantitative analyses of the critical dislocation dynamics (introduction rates and glide velocities) associated with the different process variants. These extracted values are then correlated against the ALE process variants to provide insight into the potential mechanistic roles of the different growth processes.

A 2-terminal, dual-junction, epitaxially integrated, GaAsP/Si tandem solar cell with an 3rd party certified efficiency of 23.4 % was fabricated via MOCVD growth on an ex-situ produced Si sub cell. The drastic efficiency improvement over the authors previous peer-reviewed demonstration of such a device architecture is examined. Critical advancements in top cell design to maximize short wavelength response were critical in enabling improved top cell response. An in-depth analysis of this champion tandem cell has identified key loss mechanisms which elucidate the pathway for further efficiency gains. First, voltage dependent collection efficiency in the GaAsP top cell is the primary cause of fill factor losses currently limiting efficiency. Analysis of spectrally resolved I-V measurements and analytical device modeling and indicate poor diffusion length due to elevated dislocation densities as the likely cause for the voltage dependent collection efficiency. Second, modeling for the GaAs0.75P0.25 top cell, using experimental data at multiple dislocation densities, provides quantitative understanding of the current and voltage losses associated with threading dislocations providing a clear efficiency pathway with reduction in dislocation density. Lastly Si subcell modeling identifies the pathway for further Si subcell advances over the present, simplistic design, which has yet to employ the known benefits of rear surface texture or dielectric passivation.

Threading dislocation density (TDD) is a key parameter that commonly limits the performance of epitaxially integrated III-V/Si photovoltaics. The GaP/Si epitaxial bridge is a widely studied III-V on Si integration pathway, and recent advances have realized low-10 6 cm -2 TDD in n-GaP/Si templates that can be integrated in III-V/Si PV designs amenable to efficiencies well beyond single-junction Si. However, continued development and scaling of III-V/Si PV will ultimately rely on a deeper understanding of dislocation evolution in GaP/Si and will require more process flexibility than has heretofore been demonstrated. Thus, this work demonstrates multiple pathways toward achieving-low 10 6 cm -2 TDD, through which we can gain both substantial fundamental understanding of GaP/Si integration and can achieve the needed process flexibility to enable scalable production.

This article highlights the critical role of window design on short circuit carrier collection in rear-emitter solar cells, as demonstrated through modeling and experiment using metamorphic GaAs y P 1-y . Ultimately, if the window design is not carefully considered, surface depletion caused by Fermi level pinning at the window/air interface can extend into regions of active collection resulting in a large increase in effective window/base interface recombination velocity. This was experimentally shown here to result in a potential AM1.5G photocurrent loss of 8.1 mA/cm 2 , or nearly 50%, based on integrated internal quantum efficiency (IQE). Associated IQE modeling and curve fitting indicate that the effective IRV at the GaAs 0.75 P 0.25 /Al 0.64 In 0.36 P interface is increased by multiple orders of magnitude when the window is not sufficiently thick or doped to fully contain the surface depletion to within the window layer. Calculations of the surface depletion depth as a function of doping and the surface Fermi pinning energy level provides insight into the fundamental limits of window thickness. This allows the estimation of the Al 0.64 In 0.36 P surface pinning level to be at least 1.25 eV below the conduction band edge, or in the bottom half of the bandgap.

The growth of BxGa1−xP alloys by hybrid solid/gas-source molecular beam epitaxy, with B supplied via the BCl3 gas precursor, is demonstrated. Compositional control ranging from pure GaP to B0.045Ga0.955P has thus far been achieved. Slightly tensile-strained B0.031Ga0.969P grown on nearly pseudomorphic, compressively strained GaP/Si was used to produce an effectively strain-free (0.06% tensile misfit at growth temperature) 160 nm total III–V thickness BxGa1−xP/Si virtual substrate with a threading dislocation density of <3 × 105 cm−2, at least 4× lower than comparable GaP/Si control samples. Cross-sectional transmission electron microscopy reveals that subsequent GaP overgrowth undergoes epilayer relaxation via dislocation introduction and glide at the upper GaP/B0.031Ga0.969P interface, rather than the lower GaP/Si interface, confirming the strain-balanced nature of the B0.031Ga0.969P/GaP/Si structure and its potential use as a III–V virtual substrate.

The degradation of photocarrier bulk lifetime in Si wafer substrates during the heteroepitaxial growth of III-V materials has been widely reported and is known to limit the efficiency of III-V/Si tandem solar cells. There have been prior strategies to protect Si lifetime in III-V growth chambers, but most require the use of a protective layer that must be removed in subsequent device processing. It would be advantageous for protective layers to remain an active part of the device. In this work, we demonstrate that a polycrystalline silicon (poly-Si) passivated contact can protect the minority carrier lifetime of the Si base wafer during the organometallic vapor phase epitaxy of III-V materials on silicon substrates.

The novel use of a GaAsyP1-y/GaP compressively-strained superlattice (CSS) to provide enhanced control over misfit dislocation (MD) evolution and threading dislocation density (TDD) during GaP/Si m...