The dynamics of the SPAD avalanche is a stochastic process that impacts the overall pixel performance, for high count rate and low-power applications. In this paper, we present a novel on-pixel measurement technique, the analysis of the stochastic transient responses and a statistical approach for the modeling of SPAD transient behavior.

This paper is describing structure of a Single Photon Avalanche Diode (SPAD) compact model. Using a loop architecture to describe the impact ionization phenomenon, this approach yields a closer to physics SPAD model using minimal fitting adjustments and an innovative approach, hence differentiating itself from the majority of available SPAD models.

We present a Verilog-A model accounting for the temporal avalanche buildup and its statistics in Single-Photon Avalanche Diodes (SPADs). This physics-based approach is compared to TCAD mixed-mode analyzing predictions, as well as measurements. The buildup that can be in the order of hundreds picoseconds, affects the statistical pulse width distribution, which is experimentally verified. Furthermore, we address in detail the voltage swing across the device during avalanche and its quenching, studying its impact on power consumption. This model can help a chip designer to optimize circuits for quenching the SPAD photodiode.

A Silicon photonics platform operating at 100 Gbit/s (53Gbaud-PAM4) per lane is demonstrated. Integration of 60 GHz High-Speed Photodiode and efficient High-Speed Phase Modulator into a 400G-DR4 3D test chip is shown. Extension towards 400G-FR4 is addressed by the introduction of a SiN layer allowing wideband fiber to the chip optical coupling and polarization management.

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.

A measurement setup for the characterization of very-fast transient responses in the CDM time domain is described in this paper. Experimental results are demonstrated on STI and gated diodes with a guard ring in a 65 nm and 130 nm CMOS technology. The superior behavior of gated diodes during triggering is highlighted.

High Joule heating during ESD transient is a major cause of failure in metal interconnects. In order to provide a realistic assessment of current and future interconnect performance, a scalable compact model of self heating in isolated metal lines, valid in the ESD time range (time < 100 ns), has been developed. This model turns out to be in very good agreement experimental results, and it can be used to forecast TLP I(V) characteristics of isolated metal wires.