As the drive towards the production of 100 nm CMOS devices pick up speed, the practical aspect of transistor shallow junction formation, including a large menu of process integration issues, must now be solved in a short order. The most direct path to 50 nm junction depths is through the sub-keV boron implantation and rapid thermal annealing. The material aspects of the process integration centers on: (1) CMOS devices for shallow, highly-activated and abrupt junctions (involving the choice of ion species [B, BF, B10H14, BSi2, etc.], substrate materials [ Cz, Epi, SOI], anneal conditions [ramp rate, soak time, ambient gas], etc.) and (2) Defect-dopant interactions during annealing (including surface reactions of high concentration species [B, F], diffusion and carrier trapping by background and co-implanted species [C, 0, F, etc.]. Process data for atomic and electrical activity profiles as well as defect and interface structures will be presented to illustrate progress towards understanding these complex process interactions. A particular focus will be the effects of anneal ambient and rapid temperature rise times approaching the “pike” anneal ideal.

Process integration and in-line metrology are now the key agenda items for formation of ultrashallow junctions for ultralarge scale integration devices. Integration of the complete process sequence from selection of the device layer material through introduction and activation of dopants involves dozens of interacting decisions. This article highlights some issues associated with the control of channeling, damage annealing of preamorphized and molecular ion implants, outgassing of oxygen from product wafers during rapid thermal processing cycles and conditions for control of beam divergence and doping microuniformity near gate stack structures.

The shallow doping requirements for the next 2–3 device generations can be satisfied by a combination of low-energy ion implantation and rapid-thermal anneal. However, the differing requirements of distinct types of devices preclude the definition of a single optimized process. To tailor the junction properties according to device type and geometry, requires an understanding of the effects of process parameters in both implant and anneal steps. In describing the interactions and mechanisms behind this optimization, a number of tradeoffs are highlighted: (i) The choice of implant energy and dose may be traded off against the anneal time–temperature profile. (ii) The benefits of preamorphization to reduce ion channeling are offset by the detrimental increase in transient-enhanced diffusion and dopant segregation. (iii) The use of oxygen in the anneal ambient is discussed in terms of its effects on diffusion versus dopant loss at the surface.

In order to form junctions shallower than 0.1 μm required for the source/drain extensions for 0.18 μm technology and beyond, boron ions have been implanted in pre-amorphised Si at 1 keV and doses of 1E14-1E15 cm-2 using an Applied Materials xR LEAP ion implanter. Implanted wafers were subsequently annealed in an RTP Centura to ~1 sec soak time and to temperatures between 1000-1100°C. Ramp up rates between 75°C/s and 150°C/s were examined. Junctions with depths between 40-80 nm (taken at 1E17 cm-3 SIMS B concentration) can be formed routinely with sheet resistance tuneable between 300-900 Ω/□ using Ge pre-amorphisation, and subsequent spike annealing at ramp up rates of 150°C/sec in nitrogen atmosphere. It was found that sheet resistance (Rs) is most dependent on the spike anneal temperature, while the ramp up rate appear to have a minimal effect on reducing Rs or controlling junction depth (χj ). The oxygen content in the RTA ambient is an important parameter in controlling both Rs and χj. The crystallinity of the spike annealed wafers has been evaluated using high resolution transmission electron microscopy (HRTEM)

Forming sub-100-nm junctions for source/drain designs in <180-nm devices requires optimized low-energy ion implantation and rapid thermal annealing to place dopants accurately and activate them without excessive diffusion. Boron ions were implanted at a range of low energies and implanted wafers were then annealed using various soak times, temperatures, and ramp rates. Junctions with depths of 30-70 nm (at 1 x 10(18) cm(-3)) can be formed with sheet resistance tunable between 200 and 900 Omega/square, using spike annealing at ramp rates up to 150 degrees C/sec. Oxygen content in the rapid thermal annealing ambient is also an important factor in controlling both sheet resistance and junction depth.