Large Reasoning Models (LRMs) achieve strong problem-solving through long chain-of-thought, but their deployment is constrained by the high cost of full-precision inference and growing KV cache footprints. Microscaled FP4 formats enable efficient FP4 deployment; however, fully quantizing weights, activations, and KV caches (W4A4KV4) causes severe reasoning degradation that existing PTQ and QAT fail to recover. We identify that FP4 failures concentrate on low-entropy tokens--precise symbolic commitments such as digits and operators--where quantization noise inflates sampling errors that cascade through reasoning traces. Based on this insight, we propose ReQAT, a reasoning-centric FP4 training framework with three components: (i) Trace-Aligned QAT (TAQ), which revisits identical reasoning traces to focus updates on critical low-entropy decisions; (ii) Selective Entropy Minimization (SEM), which reinforces confidence at low-entropy positions; and (iii) Q-FIT, a quantization-friendly initialization that jointly calibrates RoPE-consistent KV cache transformations to stabilize QAT. Under the same training budget, ReQAT not only recovers but surpasses BF16 fine-tuning accuracy, while delivering up to 3.9x throughput speedup on NVIDIA DGX Spark and 3.1x on B200.

Convolution is one of the fundamental operations of deep neural networks with demanding matrix computation. In a graphic processing unit (GPU), Tensor Core is a specialized matrix processing hardware equipped with reduced-precision matrixmultiply-accumulate (MMA) instructions to increase throughput. However, it is challenging to achieve optimal performance since the best scheduling of MMA instructions varies for different convolution sizes. In particular, reducedprecision MMA requires many elements grouped as a matrix operand, seriously limiting data reuse and imposing packing and layout overhead on the schedule. This work proposes an automatic scheduling method of reduced-precision MMA for convolution operation. In this method, we devise a search space that explores the thread tile and warp sizes to increase the data reuse despite a large matrix operand of reduced-precision MMA. The search space also includes options of registerlevel packing and layout optimization to lesson overhead of handling reduced-precision data. Finally, we propose a search algorithm to find the best schedule by learning from the distinctive candidates. This reduced-precision MMA optimization method is evaluated on convolution operations of popular neural networks to demonstrate substantial speedup on Tensor Core compared to the state of the arts with shortened search time.

Convolution is one of the fundamental operations of deep neural networks with demanding matrix computation. In a graphic processing unit (GPU), Tensor Core is a specialized matrix processing hardware equipped with reduced-precision warp matrix-multiply-accumulate (WMMA) instructions to increase throughput. However, it is challenging to achieve optimal performance since the reduced-precision WMMA requires many elements grouped as a matrix operand, seriously limiting data reuse and imposing packing and layout overhead on the schedule. This work proposes three techniques to enhance INT4 WMMA utilization on Tensor Cores: duplicate-aware load for increasing the reuse of convolution input, register-level packing for alleviating overhead of handling INT4 data, and data layout optimization for coalesced data transfer. The proposed INT4 WMMA optimization techniques are evaluated on convolution operations of popular neural networks to demonstrate substantial speedup on Tensor Core compared to the state of the art.

Uniform-precision neural network quantization has gained popularity since it simplifies densely packed arithmetic unit for high computing capability. However, it ignores heterogeneous sensitivity to the impact of quantization errors across the layers, resulting in sub-optimal inference accuracy. This work proposes a novel neural architecture search called neural channel expansion that adjusts the network structure to alleviate accuracy degradation from ultra-low uniform-precision quantization. The proposed method selectively expands channels for the quantization sensitive layers while satisfying hardware constraints (e.g., FLOPs, PARAMs). Based on in-depth analysis and experiments, we demonstrate that the proposed method can adapt several popular networks channels to achieve superior 2-bit quantization accuracy on CIFAR10 and ImageNet. In particular, we achieve the best-to-date Top-1/Top-5 accuracy for 2-bit ResNet50 with smaller FLOPs and the parameter size.

Uniform-precision neural network quantization has gained popularity thanks to its simple arithmetic unit densely packed for high computing capability. However, it ignores heterogeneous sensitivity to the impact of quantization across the layers, resulting in sub-optimal inference accuracy. This work proposes a novel approach to adjust the network structure to alleviate the impact of uniform-precision quantization. The proposed neural architecture search selectively expands channels for the quantization sensitive layers while satisfying hardware constraints (e.g., FLOPs). We provide substantial insights and empirical evidence that the proposed search method called neural channel expansion can adapt several popular networks' channels to achieve superior 2-bit quantization accuracy on CIFAR10 and ImageNet. In particular, we demonstrate the best-to-date Top-1/Top-5 accuracy for 2-bit ResNet50 with smaller FLOPs and the parameter size.

•Phosphate adsorption on Au substrate was investigated by in situ EC-SERS.•Under acidic condition, Au has strong tolerance to phosphate species adsorption.•ORR activities of electrodeposited PtAu alloys were tested in the presence of PA.•PtAu catalysts exhibited better ORR activity than pure Pt in the presence of PA.

NiCu alloys have been suggested as potential candidates for catalysts in glucose oxidation. In this study, NiCu alloys with different compositions were prepared on a glassy carbon substrate by changing the electrodeposition potential to examine the effect of Ni/Cu ratios in alloys on catalytic activity toward glucose oxidation. Cyclic voltammetry and chronoamperometry showed that NiCu alloys had higher catalytic activity than pure Ni and Cu catalysts. Especially, Ni59Cu41 had superior catalytic activity, which was about twice that of Ni at a given oxidation potential. X-ray analyses showed that the oxidation state of Ni in NiCu alloys was increased with the content of Cu by lattice expansion. Ni components in alloys with higher oxidation state were more effective in the oxidation of glucose.

Heterogeneous computing that combines a traditional CPU architecture with an accelerator has become a popular architecture. Memory modelling design decisions affect not only architecture designs but also programming models. Hence, comparing them is very challenging and not all design spaces have been explored. Although a unified memory address space that is fully coherent and strongly consistent across the entire memory system would be the ideal case, because of scalability and complexity, less ideal designs have been proposed. In this paper, we explore various design options quantitatively and qualitatively. Our results suggest that maintaining a separate memory model for each architecture and having a partially shared memory space provide the most design options in both programming models and architecture designs.

Graphics Processing Units (GPUs) are very popular for both graphics and general-purpose applications. Since GPUs operate many processing units and manage multiple levels of memory hierarchy, they consume a significant amount of power. Although several power models for CPUs are available, the power consumption of GPUs has not been studied much yet. In this article we develop a new power model for GPUs by utilizing McPAT, a CPU power tool. We generate initial power model data from McPAT with a detailed GPU configuration, and then adjust the models by comparing them with empirical data. We use the NVIDIA's Fermi architecture for building the power model, and our model estimates the GPU power consumption with an average error of 7.7% and 12.8% for the microbenchmarks and Merge benchmarks, respectively.

The activities of Au-modified Cu electrodes toward glucose oxidation are evaluated according to their fabrication conditions and physico-chemical properties. The Au-modified Cu electrodes are fabricated by the galvanic displacement of Au on a Cu substrate and the characteristics of the Au particles are controlled by adjusting the displacement time. From the glucose oxidation tests, it is found that the Au modified Cu has superior activity to the pure Au or Cu film, which is evidenced by the negative shift in the oxidation potential and enhanced current density during the electrochemical oxidation. Though the activity of the Au nanoparticles is a contributing factor, the enhanced activity of the Au-modified Cu electrode is due to the increased oxidation number of Cu through the electron transfer from Cu to more electronegative Au. The depletion of electron in Cu facilitates the oxidation of glucose. The stability of the Au-modified Cu electrode was also studied by chronoamperometry.

We implemented a decoder for low-density paritycheck (LDPC) codes intended for NAND flash memory error correction. Since the input is given as a binary valued signal, a hard-decision bit flipping based decoding algorithm is used. To simplify the hardware, a circular shiftregister based partially parallel decoding architecture is employed. With this architecture, it is very easy to increase the throughput or reduce the power consumption by raising the parallel factor. The implemented decoder, which employs a (4161, 3431) projective geometry-based LDPC code, operates at 400 Mbit/s throughput with the parallel factor of 32. Synthesized using a 0.25㎛ CMOS technology, the proposed decoder consumed 208 ㎽ with 2.5 V supply.