Dynamic vibration absorbers (DVAs) can effectively suppress unwanted vibrations in primary structures. However, traditional DVAs struggle to adapt to variable operating requirements due to their fixed damping and susceptibility to wear. In this paper, a tunable DVA based on Electromagnetic Shunt Damping (EMSD) is proposed. By establishing a nonlinear electromechanical coupling model that considers spatial magnetic field distribution, the analytical relationship between the induced electromotive force (EMF) and the electromagnetic damping force is derived. Subsequently, the Harmonic Balance Method (HBM) is employed to determine the steady-state response of the system under harmonic excitation, and the accuracy of the theoretical model is verified through Runge-Kutta numerical simulations. Based on the principle of periodic average energy dissipation equivalence, an equivalent linearization tuning strategy is proposed to transform the nonlinear damping into linear equivalent damping. Furthermore, the Newton iteration method is employed to achieve optimal parameter matching for the damped main system, effectively overcoming the limitations of the traditional Den Hartog fixed-point theory. Finally, numerical studies are performed to evaluate the applicability and limitations of the proposed optimal design method for the EMSD-DVA, with particular attention given to the optimal design conditions under varying geometric parameters. This study provides theoretical guidance for the design and tuning of EMSD-DVA.

Gallium oxide (Ga2O3), as an emerging ultrawide bandgap semiconductor materials, has demonstrated significant potential in solar-blind ultraviolet photodetection. This study prepared aluminum nanoparticles (NPs) to significantly improve the performance of amorphous Ga2O3(a-Ga2O3) metal-semiconductor-metal (MSM) solarblind ultraviolet photodetectors. Under a 10 V bias voltage, the Al-NPs/a-Ga(2)O(3 )device achieve a peak responsivity (R) of 2.24 & times; 10(3)A W-1 , an external quantum efficiency (EQE) of 1.1% & times; 10(6)%, and a specific detectivity (D-& lowast; ) of 1.4 & times; 10(12) Jones, corresponding to improvements of 597%, 1867%, and 611%, respectively, compared to pristine a-Ga(2)O(3 )photodetectors without Al-NPs. These enhancements are mainly ascribed to the localized surface plasmon resonance (LSPR) effect generated by the Al-NPs, which effectively enhances the light absorption and carrier excitation, thereby improving the ultraviolet signal detection capability of the device. This work provides a simple, low-cost, and easily reproducible method that offers new ways and possibilities to optimize the performance of optoelectronic devices

Hafnium oxide-based resistive switching (RS) devices are promising candidates for next-generation nonvolatile memories because of their ability to integrate into silicon electronics. However, irreversible and unidirectional movements of oxygen vacancies in functional oxide in memristors limit the improvement of ON/OFF ratio and endurance simultaneously as well as the highest working temperature up to 300 degrees C. Here, we design varistructure RS devices through oxygen vacancy engineering and dynamical redox of Ta. The ON/OFF ratio and the endurance are largely co-improved due to dynamical redox of Ta at the interfaces. Compared to all current RS memories, it cumulatively demonstrates high endurance (10(5)), retention (10(4) s), ON/OFF ratio (10(4)-10(6)), operation speed (75 ns), and low write voltage (2 V). Remarkably, the RS devices remain stable up to 300 degrees C.

Gallium nitride high electron mobility transistors (GaN HEMTs) are widely used in DC-DC converters because of their advantages such as fast switching speed and low on-resistance, but they are very sensitive to parasitic inductance. This paper presents a novel PCB layout of GaN devices with ultra-low power loop parasitic inductance. The proposed layout is to embed the decoupling capacitors horizontally into the PCB board, reducing the power loop area and the parasitic inductance of the overall power loop. In order to verify the feasibility of the proposed layout, theoretical analysis and simulation verification are carried out in detail. A 12 V-to-3.3 V GaN-based buck experimental prototype is designed and tested. The experiment demonstrates that power loop inductance of the embedded capacitors layout is 0.051 nH and drain-source voltage overshoot is 0.12 V only 1% at 1 MHz switching frequency, which is reduced by 49% and 7.3% compared with the current state-of-art double-sided layout (0.1 nH), respectively.

In data center applications where most power supplies are in light-load operation, hence optimizing light-load efficiency is immensely crucial. In this article, a fractional-turn planar transformer with an elliptical core is proposed, which reduces the eddy loss of the core and improves the light-load efficiency. This structure also reduces the magnetic core profile and improves the power density. Magnetic loss theory, winding configuration and core optimization were analyzed in detail. Finally, a detailed optimization process about transformer is carried out based on finite-element analysis, and two 1 MHz 380 V-12 V 720 W LLC converters are designed based on the conventional fractional-turn transformer and the proposed fractional-turn transformer, respectively.

In this study, the parameters of a normally-OFFvertical GaN junction field-effect transistor (JFET) weresimulated to analyze the breakdown mechanisms of thedevice. Key factors, including the electron concentration ofthe channel (N-channel), hole concentration of the p+ region(NP-region), channel length (L-channel), and channel width(W-channel), were evaluated for their influence on the elec-trical characteristics and breakdown mechanisms of thedevice. The findings reveal the following: 1) JFET devicesexhibit three breakdown mechanisms-drain-to-gate anddrain-to-source breakdowns, and the coexistence of both;2) under the drain-to-source breakdown mechanism, thedevice experiences higher leakage current and severebreakdown voltage (BV) degradation; 3) when the break-down mechanism is drain-to-gate, the device demonstratessuperior breakdown characteristics, with low leakage cur-rent and highBV, an albeit with increased specificON-resistance (Ron,SP); and 4) when both mechanismscoexist, the device exhibits increased leakage current whilemaintaining a highBV. Concurrently, the forward charac-teristics improve significantly, enhancing the power figureof merit (FOM). To improve the overall device performance,a gradient doping channel JFET (GD-JFET) device wasproposed, in which a three-layer gradient doping chan-nel was adopted to balance the tradeoff between FOMand threshold voltage (VTH). Compared to a conventionalJFET (C-JFET), theVTHof GD-JFET increased by 15.8%,whereas the FOM increased by 12.0%. These findings indi-cate that the

Ga(2)O(3 )exhibits unique advantages in photodetection due to its high absorption coefficients for deep ultraviolet (DUV) and X-ray photons, excellent radiation hardness, and remarkable stability. Researchers have been focusing on developing novel, low-cost, high-performance detectors. Here, a cost-effective and facile mist chemical vapor deposition (Mist-CVD) method for the high-quality epitaxial growth of Ga(2)O(3 )with a full width at half maximum of 0.63 degrees was employed, ultimately achieving thin-film device with exceptional optoelectronic performance. The fabricated device achieves exceptional sensitivities, including a high R of 112 AjW @ 254 nm illumination and a maximum sensitivity of 2.78 & times;10(4) mu C & sdot;Gyair(-1)& sdot;cm(-2) under X-ray irradiation. Furthermore, the device exhibits a rapid recovery time (tau d1=16 ms). This work comprehensively demonstrates the feasibility of growing Ga(2)O(3 )via Mist-CVD and highlights the strong competitiveness of Ga(2)O(3 )in ultraviolet DUV and X-ray detection applications.

In this work, we demonstrate fully strained GaN channel high electron mobility transistors (HEMTs) with superlattice barriers on AlN-on-sapphire templates by plasma-assisted molecular beam epitaxy. Here, ferroelectric Sc0.18Al0.82N epilayers are introduced into the heterostructure to engineer the device performance. Instead of the conventionally thick AlN buffer, an ultrathin Sc0.18Al0.82N layer is positioned between the AlN template and the GaN channel to effectively suppress the leakage at the interface between the secondary epilayers and the AlN template, realizing fully strained epitaxial structures less than 60 nm. Besides, a Sc0.18Al0.82N layer serves as a part of the superlattice barrier with well-defined interfaces, which results in a stronger polarization effect and larger conduction band offset and thus a high carrier density of 3.12 × 1013 cm−2. The processed GaN HEMT engineered by Sc0.18Al0.82N epilayers exhibits direct-current transfer characteristics with an on/off current ratio of ∼106 and distinct counterclockwise ferroelectric hysteresis windows, with a widely tunable threshold voltage ranging from −6.3 to −2.7 V. The fabricated device with a 180-nm T-shaped gate and gate-drain space of 1.5 μm achieves a breakdown voltage of 80 V, a cutoff frequency of 32 GHz, and a maximum oscillation frequency of 70 GHz, respectively. This work provides a new approach for developing next-generation multifunctional transistors on an ultrawide bandgap AlN platform through synergistically integrating ferroelectric gate modulation with a superlattice barrier, offering a promising candidate for highly reliable microwave power electronics with tunable switching characteristics.

Scandium-doped aluminum nitride (ScAlN) has emerged as a wide-bandgap ferroelectric material with exceptional potential for next-generation electronic devices due to its tunable polar properties, high breakdown field, and strong spontaneous polarization. Compared to conventional nitride semiconductors, there is still a gap in a comprehensive overview of the connection between material growth and device application. Herein, we summarize the development in material growth, fundamental properties, and device applications of ScAlN. We evaluate growth techniques and highlight their impact on crystallinity, defect density, and underlying mechanisms. More importantly, we discuss the integration of ScAlN and challenges in the advanced devices, including power electronic devices, artificial synapses, resonators, and filters. This perspective provides a strategic insight for future research, aiming to accelerate the development of high-performance, multifunctional ScAlN-based devices.

In this work, we reveal the phenomenon of incomplete coalescence in the direct epitaxial growth of GaN films on AlN substrates, highlighting the critical role of interface modulation in achieving high-quality GaN growth. Interface modulation enhances the diffusion of adsorbed atoms, thereby reducing defect formation. This approach enables layer-by-layer growth at low Ga source flux. The results significantly improve the crystal quality of GaN on AlN substrates, paving the way for superior performance in AlN-based AlGaN/GaN HEMT devices. This HEMTs attain a saturation current density of 965.6 mA/mm, a peak transconductance of 200 mS/ mm, and a breakdown voltage reaching 1986 V for LGD = 12.5 mu m. This confirms the strategy's practicality and technological significance of interface modulation strategies and demonstrate the great potential for fabricating high-power devices on AlN substrates.

Abstract This paper investigates the performance enhancement of vertical GaN trench MOS barrier Schottky (TMBS) rectifiers through the integration of an Al 2 O 3 /SiO 2 stacked dielectric layer. By employing a 30 nm plasma-enhanced atomic layer deposition Al 2 O 3 high-k interlayer as a dielectric, the electric field crowding at the trench corners is significantly redistributed and mitigated. Compared to the reference planar Schottky barrier diode with a breakdown voltage ( BV ) of 360 V and the conventional SiO 2 -only TMBS with a BV of 550 V, the proposed Al 2 O 3 /SiO 2 TMBS rectifier achieves a higher BV of 820 V, representing a 2.3-fold improvement over the planar structure. Simulations reveal that the high-k Al 2 O 3 interlayer effectively modulates the electric field distribution at the trench bottom, significantly mitigating localized field crowding at the corners and preventing premature breakdown. Furthermore, the device demonstrates a high ON/OFF current ratio of ∼5 × 10 10 and excellent dynamic reliability, with a dynamic R on, sp increase of only 15% after 400 V/1 s stress. These results underscore the critical role of high-k dielectric engineering in optimizing the power figure of merit and reliability of GaN-based vertical power rectifiers.

In this work, a δ-doped p-GaN/u-GaN/AlGaN multi-channel heterostructure is proposed and fabricated by metal-organic chemical vapor deposition (MOCVD). Hall measurement results indicate that the optimized multi-channel structure achieves a record-low sheet resistance of 7529 Ω/□ by MOCVD. The AlGaN/GaN/AlGaN sandwich structure strengthens the quantum confinement for holes and leads to a high polarization-induced hole density of 8.80 × 1013 cm−2. By spatially segregating charge carriers across multiple channels, the multi-channel architecture mitigates inter-carrier scattering and achieves a carrier mobility of 9.42 cm2/V·s. Besides, employing an InGaN layer as the ohmic contact layer significantly reduces the sheet resistance. This achievement provides an important material foundation for the development of high-performance GaN-based p-channel field-effect transistors.

In this Letter, a monolithic heterogeneous integration platform based on a p-GaN/AlGaN/GaN epilayer is demonstrated, where Si pMOSFETs and p-GaN gate GaN HEMTs are co-integrated on the same Si substrate using the transfer printing and bonding technology. The fabricated Si–GaN hybrid CMOS inverter consisting of a Si pMOSFET and a p-GaN gate GaN HEMT exhibits excellent symmetry in noise margins (NML and NMH) and rise/fall times. A high peak voltage gain of 38 V/V is achieved with an ultralow hysteresis of 0.01 V, and the switching threshold remains close to VDD/2 with a drift of less than 0.25 V at 150 °C, while both NML and NMH retain more than 49% and 30% of VDD, respectively. Moreover, the integrated p-GaN gate GaN HEMTs maintain exceptional stability after complex compatibility processing, including an ultralow VTH hysteresis of 0.02 V, excellent gate reliability (ΔVTH < 0.5 V under stress), a small VTH shift of <0.12 V at 150 °C, a breakdown voltage of 1.88 kV, and a well-suppressed dynamic RON degradation (<30% at 1200 V). These results demonstrate that the optimized SiN insertion bonding layer and post-annealing process play a key role in mitigating stress mismatch, suppressing parasitic channel effects, and reducing dynamic RON degradation, achieving the outstanding high-temperature stability, noise immunity, and balanced driving capability of the Si–GaN integrated platform, which are essential for reliable operation in harsh environments. It is demonstrated that the proposed platform offers superior stability for both signal processing and power switching under high-temperature and high-voltage conditions, representing a promising solution for monolithic heterogeneous integrated power-driver chips.

To address the critical bottlenecks of low computational efficiency and excessive memory consumption in the electromagnetic (EM) simulation of 3-D complex microwave devices with the conventional finite element method (FEM), a hybrid finite element physics-informed neural network (HFE-PINN) is proposed in this article for efficient and high-precision 3-D EM simulation. A cascaded framework combining finite element discretization and physics-informed neural networks (PINNs) is employed. The Helmholtz equation is discretized into a sparse linear system by the finite element discretization module. A distributed subnetwork structure is utilized in the PINN module, with the midpoint coordinates of edges as inputs and the predicted solution of the finite element matrix equation as outputs. The physics-constrained loss function is minimized via the L-BFGS optimization algorithm, so that the predicted solution is driven to converge quickly to the true solution of the EM governing equation. Furthermore, the convexity of the HFE-PINN loss function is rigorously proved theoretically, which ensures that the global optimal solution can be obtained by the L-BFGS algorithm. Numerical examples demonstrate that the proposed method achieves high-precision EM simulation of arbitrarily complex microwave devices without labeled data, and outperforms the conventional FEM in computational efficiency and memory usage.

In this work, a novel Schottky-gated p-channel GaN field-effect transistor (PFET) with a tunable n-GaN sub-gate layer is investigated. Terminal-current analysis under the actual drain-bias condition shows that the gate-current contribution remains limited within the defined effective operating range of VGS ≥ −3.2 V, whereas gate-related current becomes significant at more negative gate biases. Carrier-resolved and spatial current analyses further confirm that, within this operating range, the drain current is predominantly carried by holes through an interfacial hole channel near the p-GaN/AlGaN heterointerface. Benefiting from the intentionally introduced p–n junction beneath the groove gate, the built-in electric field effectively depletes the p-GaN channel, enabling a robust transition from depletion-mode to enhancement-mode (E-mode) operation. By precisely scaling the n-GaN layer thickness (0–5 nm) and donor concentration (3.0 × 1017 cm−3 to 3.0 × 1019 cm−3), the buried p-n junction modulates the depletion condition and hole distribution beneath the gate. The optimized device exhibits a significantly improved subthreshold swing (SS) of 348 mV/dec, while maintaining a stable ION/IOFF ratio on the order of 102. This tunable sub-gate architecture provides a highly flexible platform for optimizing E-mode GaN PFETs, showing great promise for high-performance complementary logic applications.

In this study, a memristor with an Al/aluminum nitride (AlN)/Pt structure was fabricated, and the coexistence of bipolar resistance switches (BRS) and unipolar resistance switches (URS) was observed. The device exhibits a high resistance state (HRS) with a resistance value exceeding 10(5)Omega for both switching modes. Remarkably, the device demonstrates excellent retention characteristics, maintaining stability for up to 10(4) s. Endurance testing revealed that the device can sustain over 10(3) DC switchingcycles, with resistance switching ratios greater than 10(2) in BRS mode and exceeding 10(3) in URS mode. To investigate the underlying conduction mechanisms, we performed conductive atomic force microscopy (C-AFM) measurements coupled with current-voltage (I-V) curve fitting analysis. Our findings reveal that the low-resistance state (LRS) conduction is governed by the formation of conductive filaments (CFs), while the forming process exhibits carrier transport characteristics consistent with Schottky emission. Both BRS and URS modes in the HRS regime demonstrate space-charge-limited current (SCLC) conduction behavior. Furthermore, temperature-dependent resistance measurements of the LRS suggest that the CFs are predominantly composed of Al atoms, providing crucial insights into the atomic-scale switching mechanisms in this memristive system.

This paper presents a 3-D integrated hybrid package using phase change vapor chamber (VC), flexible printed circuit (FPC), direct plating copper (DPC) and diamond. This package improves vertical space utilization and reduces profile height. A 23×31×4.7 mm double-sided cooling half-bridge power module with integrated gate drivers is fabricated. Compared with double-sided ceramic module, the junction temperature can be reduced by 30% at a power loss of 60W. The inductance of the power loop was reduced to 0.75 nH. This work optimizes the overall performance of GaN power module, balancing integration level with electrical and thermal performance.

Traditional GaN materials inevitably exhibit lattice mismatch and differing thermal expansion coefficients during epitaxial growth, which often leads to a sharp increase in dislocation density and interface defects. This results in severe current collapse, degraded high-frequency performance, and reliability degradation in GaN high electron mobility transistor (HEMT) devices, representing one of the key bottlenecks facing GaN-based HEMT RF devices. Van der Waals epitaxial bonding between BN and GaN effectively suppresses dislocations and relieves material stress, playing a crucial role in enhancing the high-frequency performance and reliability of GaN HEMT devices. This paper fabricates AlGaN/GaN HEMT devices grown on BN buffer layers using van der Waals epitaxy. Test results indicate that compared to conventional devices without a BN buffer layer, not only has the on-resistance been reduced by 40% and the peak transconductance increased by 54%, but the maximum output current has also been boosted by 67%. Under strong negative gate voltage stress conditions, its performance significantly outperforms conventional devices, with a current collapse ratio of only 9.2%. During the pulse width reduction from 200 ms to 100 mu s, only a minimal drift of approximately 0.09 V occurs. Under high-temperature conditions (125 degrees C), the current collapse ratio is only 31%, with smaller reductions in transconductance and negative drift of V-th.The overall degradation is significantly lower than that of conventional AlGaN/GaN HEMT devices based on epitaxial systems, demonstrating excellent high-temperature dynamic stability. Additionally, RF performance improved, with f(T) increasing from 48 to 90 GHz and f(max) rising from 114 to 133 GHz. This work fully demonstrates this interface optimization strategy simultaneously enhances carrier transport, suppresses trap effects, and improves RF performance, providing an effective pathway for realizing high-frequency, high-power, and highly reliable GaN HEMTs.