This study compares the scalability of charge-trap metal-oxide-semiconductor field-effect transistors (CT-MOSFETs) and charge-trap tunnel field-effect transistors (CT-TFETs) for high-accuracy analog vector-matrix-multiplication (VMM) operations for the first time. Featuring stronger gate-controllability, CT-TFETs demonstrate better channel length modulation ( $\lambda \text {)}$ and analog weight level difference ratio ( $\Delta {I}_{\text {W}}$ / ${I}_{\text {W{0}}}\text {)}$ than those of CT-MOSFETs in both long and short gate length ( ${L}_{\text {G}}\text {)}$ cases (500 and 65 nm), maintaining low VMM error in the scaled case. Consequently, CT-TFETs show ~6.25× higher tolerable IR drop range and 11-% higher MNIST classification accuracy than CT-MOSFETs in the 65-nm ${L}_{\text {G}}$ case.
Event-based vision sensors convert light intensity variations into asynchronous spike signals, featuring high temporal resolution and low data redundancy. However, event-driven detection technology is rarely applied to solar-blind ultraviolet (UV) detection. In this work, we demonstrate a 254 nm solar-blind UV event sensor based on $\beta $ -Ga2O3, which combines photodetectors with dual-channel complementary event-processing circuits. The device generates dual-polarity spike outputs whose amplitudes positively correlate with incident irradiance, with an event response time below 7.5 ms. A bias of 10 V yields an optimal analog threshold of 2.33 mW/cm2, balancing noise suppression and detection sensitivity without additional external filters. Array-level simulations based on experimental parameters verify reliable edge detection and motion tracking under dynamic gesture scenarios. This work proves the great potential of $\beta $ -Ga2O3 for neuromorphic solar-blind UV sensing, and offers a feasible solution for high-speed dynamic UV monitoring.
In this study, we present a novel simulation framework for negative capacitance field-effect transistors (NCFETs), rigorously incorporating position- and gate-bias-dependent partial polarization behavior in ferroelectric (FE) layers. While previous theoretical approaches primarily assumed fully polarized FE (FPFE) states, our method integrates Poisson’s equation, the nonequilibrium Green’s function (NEGF) formalism, and a minor loop FE polarization model to accurately simulate partially polarized FE (PPFE) states, which occur frequently under realistic operating conditions. Our results demonstrate that NCFETs operating under PPFE states demonstrate worsened subthreshold swing (SS) and drain-induced barrier lowering (DIBL) compared to the FPFE case. Specifically, we reveal that FPFE assumptions tend to overestimate the steepness of the switching behavior and illustrate how the magnitude of polarization distinctly affects the gate control and spatial conduction band profile. We further investigate and compare the impact of FE thickness and channel length on DIBL in FPFE- and PPFE-NCFETs, offering critical insights for the optimization of FE-based ultralow-power electronics.
A phenomenological mathematical (PM) model is proposed to describe the current–voltage ( $I$ – $V$ ) characteristics of silicon (Si) p-n junction diodes, based on a self-feedback mechanism. The self-feedback principle assumes that the rate of change of a physical quantity depends only on the quantity itself, i.e., $\text {d} {y}/\text {d} {x}={f}({y})$ . Experimental $I$ – $V$ measurements are performed under both forward and reverse bias conditions. In the forward bias region, the carrier concentration growth rate $\text {d} {n}/\text {d} {V}$ is modeled as proportional to ${n}+{n}_{{0}}$ , where ${n}+{n}_{{0}}$ denotes the background carrier concentration, accounting for diffusion dominated current transport. In the reverse-bias regime, the $I$ – $V$ behavior is divided into three distinct stages governed by different carrier dynamics: 1) Stage I: $\text {d} {n}/\text {d} {V} \propto {n}_{{1}-{n}}$ , where ${n}_{{1}}$ represents the saturation carrier concentration, reflecting minority carrier diffusion; 2) Stage II: $\text {d} {n}/\text {d} {V} \propto {n}$ , corresponding to avalanche multiplication; and 3) Stage III: $\text {d} {n}/\text {d} {V} \propto {n}_{{1}}+\delta $ , with $\delta \gt {0}$ as an empirical constant, capturing the effects of band-to-band tunneling and the steeper-than-avalanche rise in carrier concentration. Analytical expressions derived from the PM model exhibit excellent agreement with experimental data across the entire I–V curve. In contrast to conventional models that rely on idealized assumptions-such as constant carrier mobility or abrupt junction approximation-the proposed PM model captures the nonlinear evolution of carrier concentration through a self-feedback framework, enabling a unified description of both forward and reverse $I$ – $V$ characteristics. This work provides new insights into the mechanisms underlying charge transport in semiconductor diodes.
A silicon-on-insulator (SOI) power device with a self-charge-balanced low-resistance conductive layer (S-LC) is proposed and experimentally demonstrated in this article. A self-charge-balance of S-LC is established between the additional surface positively ionized donors and the negative MIS-coupled charges, thereby eliminating the dependence on additional n-type doping relative to p-type doping. The S-LC eliminates the inevitable current-path reduction and premature inner breakdown in conventional low-resistance conductive layers based on p-n junctions. The additional n-type doping region, requiring no extra mask or lithography process, serves as a low-resistance conductive layer, thereby reducing the specific on-resistance ${R}_{\text {on,sp}}$ . Consequently, a normalized conduction factor $\eta _{\text {C}}$ , which is consistently greater than one, is attained while maintaining a high breakdown voltage ${V}_{\text {B}}$ . In experiments, the S-LC introduced an additional n-type doping dose of $1\times 10^{{12}}$ ${\mathrm {cm}}^{-{2}}$ . Then, a measured low ${R}_{\text {on,sp}}$ of 4.7m $\Omega {\,}\cdot $ cm2 was observed in the S-LC device under a ${V}_{\text {B}}$ of 290 V, realizing a high figure of merit $\textit {FOM} = {V}_{\text {B}}^{{2}}$ / ${R}_{\text {on,sp}}$ of 17.89 MW/cm2 and a reduction of 70.5% when compared with the theoretical value of the triple RESURF technology under the same ${V}_{\text {B}}$ . Moreover, the S-LC lateral double-diffused MOSFET (LDMOS) has successfully passed a series of reliability tests, including high-temperature reverse-bias (HTRBs) and high-temperature gate-bias (HTGBs) tests.
Sub-10 nm nanoelectronics scaling demands channel materials combining superior electrostatic control, high mobility, and low power consumption. Tungsten diselenide ( ${\mathrm{WSe}}_{{2}}\text {)}$ has emerged as a premier 2-D candidate due to its tunable bandgap, atomic thickness, and ambipolar transport. This review systematically examines recent WSe2 field-effect transistor advancements across five core domains: architectures, doping, contact engineering, reliability, and applications. Advanced configurations, including dual-gate FETs, vertically stacked complementary FETs (CFETs), and steep-slope variants, significantly enhance scalability and energy efficiency. Surface charge transfer (SCT) and substitutional doping enable stable unipolar operation while preserving gate control. Contact optimization via van der Waals (vdW) interfaces and alloyed electrodes effectively mitigate Fermi-level pinning (FLP) and reduces contact resistance ( ${\mathrm{R}}_{\text {C}}\text {)}$ . Interfacial passivation with h-BN and plasma treatments robustly suppresses charge trapping and threshold voltage hysteresis. Finally, WSe2-FETs are positioned for transformative roles in low-power CMOS, flexible electronics, biosensors, neuromorphic computing, and optoelectronics, alongside key commercialization pathways.
Visual perception plays a fundamental role in human decision-making and behavior, driving sustained efforts to develop devices that emulate the biological visual system. Conventional machine vision systems based on complementary metal–oxide–semiconductor (CMOS) technology, however, suffer from high power consumption and significant processing latency. In this work, we demonstrate a fully solution-processed indium gallium zinc oxide (IGZO)-based photoelectric thin-film transistor (TFT) that integrates visual sensing and synaptic functions, thereby mimicking retinal photoreceptors and visual cortical synapses. The fabricated device exhibits excellent electrical characteristics, including a high on/off current ratio of ${1}.{58}\times {10}^{{6}}$ , a field-effect mobility of 37.4 cm ${}^{{2}}\cdot $ V ${}^{-{1}}\cdot $ s ${}^{-{1}}$ , a subthreshold swing of ~0.29 V/dec, and a threshold voltage of 0.75 V. Through tunable sensing-synaptic integration, the transistor can simulate light-triggered reflexive responses analogous to the orbicularis oculi muscle contraction. Moreover, the photoresponse of the IGZO channel can be modulated by the gate voltage, which serves as an emotion-like external parameter to regulate visual perception and exhibit visual adaptation. Furthermore, we construct a retina-inspired phototransistor reservoir computing (RP-RC) system, which successfully performs language learning tasks by classifying videos containing English words with identical endings but distinct spatiotemporal dynamics. Classification accuracies of 97.6% and 93.6% are achieved under noise coefficients of 0.15 and 0.30, respectively, confirming the potential of this device as a promising platform for neuromorphic vision systems.
In this work, an ErTi ${}_{x}$ O ${}_{y}$ /hafnium aluminum oxide (HfAlO)/Si gate-stack structure was designed and fabricated. The modulation effect of atomic layer deposition (ALD)-derived HfAlO passivation layer thickness on interface chemistry, electrical properties, and their reliability was systematically explored. The results reveal that the HfAlO passivation layer restrains interfacial oxidation and reduces interface trap density. The sample with ten ALD cycles (2.2 nm HfAlO) presents an interfacial Si ${}^{{4}+}$ /Si ${}^{{2}+}$ total fraction of 21.8% and a surface rms roughness of 0.40nm. It delivers excellent electrical performance, including a dielectric constant of 22.37, a low leakage current density of ${3}.{72}\times {10}^{-{8}}$ A/cm2, and an interface state density of ${2}.{98}\times {10}^{{12}}$ cm ${}^{-{2}}\cdot $ eV ${}^{-{1}}$ , along with the maximum accumulation capacitance and negligible frequency dispersion of capacitance–voltage ( $C$ – $V$ ) and conductance–voltage ( $G$ – $V$ ) curves. Moreover, this moderate-thickness passivation layer greatly improves the thermal stability and time-dependent stability of the gate-stack. This work offers experimentally supported guidance for optimizing the high- $k$ gate dielectric and its interface in CMOS devices.
Ultrascaled transistors with monolayer (ML) and bilayer (BL) MoS2 channels were fabricated using a metal-bridging-free (MBF) process platform. During fabrication, the MoS2 channels were prepared using the transfer process. We employed I-line photolithography and a photoresist (PR) trimming process to reduce the channel length (L ${}_{\text {CH}}\text {)}$ of the transistors. The experimental results demonstrate that LCH can be down to 20 nm with good dimensional control and uniformity. By comparing ML and BL transistors of the same nominal LCH, it is observed that the BL devices exhibit a higher on-state current and reduced contact resistance. Nonetheless, in the BL devices, interfacial air gaps between the two MoS2 layers were introduced during the transfer, resulting in poorer uniformity in the device characteristics.
This study investigates electromigration (EM) degradation in copper redistribution layers (RDLs) under electrothermal loading through high-current-density experiments, microstructural characterization, and phase-field (PF) simulations. The resistance increase showed strong temperature dependence consistent with an Arrhenius-type trend, rising by 0.91% after 16h at $55~^{\circ }$ C and by 20.43% after 3 h at $175~^{\circ }$ C. Without temperature control, resistance increased by 384.71% within 207 s at ${2}.{1} \times {10}^{{6}}$ A/cm2. Representative electron backscatter diffraction (EBSD) observations showed grain coarsening, with the mean grain size increasing from 1.31 to $1.71~\mu $ m, together with enrichment near the [101] orientation. Under a representative coupled condition, the thermomigration-to-EM flux ratio was approximately 2.54, indicating an enhanced thermomigration contribution while the electron-wind force remained important. PF simulations further showed that temperature gradients promote void morphological instability and that diffusivity heterogeneity facilitates preferential void nucleation. Overall, RDL degradation evolves from gradual resistance growth to rapid structural failure through the coupled effects of EM, thermomigration, and Joule-heating feedback.
This work reports the radiation effects on gallium nitride (GaN) p-FETs and complementary logic (CL) circuits. Co ${}^{{60}} ~\gamma $ -rays are used as the radiation source. For the p-FET, after being radiated with an accumulated dose of 1 Mrad, the threshold voltage ( ${V}_{\text {th}}\text {)}$ shifts negatively from −0.5 to −1 V, which is attributed to radiation-generated holes. The on-resistance ( ${R}_{\text {on}}\text {)}$ increases from 1.04 to 1.13 k $\Omega \cdot $ mm. Subsequently, the p-FET underwent a 168-h room-temperature (RT) anneal, and its ${V}_{\text {th}}$ and ${R}_{\text {on}}$ recover to −0.5 V and 1.08 k $\Omega \cdot $ mm, respectively. For the n-FET, the ${V}_{\text {th}}$ remains unchanged at 1.3 V after radiation. The ${R}_{\text {on}}$ increases from 6 to $6.8~\Omega \cdot $ mm, and shows no recovery after 168-h RT annealing; the degradation in ${R}_{\text {on}}$ is attributed to radiation-induced defects in the access region. As for the CL inverter, after being radiated up to an accumulated dose of 1 Mrad, a rail-to-rail voltage swing ( ${V}_{\text {swing}}\text {)}$ of 6 V, a high noise margin (NM ${}_{\text {H}}\text {)}$ of 4.7 V, and a low noise margin (NM ${}_{\text {L}}\text {)}$ of 1.09 V are maintained. These results demonstrate the superior radiation tolerance of GaN CL circuitry for radiation-prone applications.
High-power microwave and pulsed power applications impose stringent dual requirements on the output power density and withstand voltage of a photoconductive semiconductor switch (PCSS). As a key structural parameter, interelectrode spacing governs the trade-off between these two critical performances. Conventional studies have mainly focused on macroscopic electric field distribution, whereas the microscopic mechanism of inhomogeneous carrier transport under optical excitation remains poorly understood. This work investigates high-purity 4H-SiC PCSS with coplanar electrodes using experiment and simulation. The experimental results show that the output pulse amplitude of the 1 mm-spacing PCSS is approximately 1.9 times that of the 5 mm under the same bias electric field. The simulation results indicate that a longer electrode spacing forces photogenerated carriers to pass through the nontriggered region, increasing the transit time and bulk recombination, thereby reducing the effective charge carriers. A smaller electrode spacing will lead to an increase in the proportion of electric field distortion caused by space charge effects, resulting in a decrease in the average effective electric field. This study provides design guidance for the coordinated control of output power density and withstand voltage of 4H-SiC PCSS.
Resonators with high quality factors (Q-factors) serve as fundamental building blocks in terahertz technology, enabling promising applications in biosensing and on-chip integrated circuits. Although array resonators excited by spatial waves enable high-Q resonance with larger physical and electrical sizes, attaining a high Q-factor in a single on-chip integrated resonator using guided wave excitation at the subwavelength scale remains a significant challenge. In this work, we propose a complementary spoof localized surface plasmon (SLSP) structure that synthetically optimizes both absorption and radiation losses, thus achieving a high Q-factor. The design incorporates a coupled SLSP configuration to enhance the mode confinement, effectively minimizing the radiation loss. The complementary structure further enables the currents to flowthrough a broader metal area, which helps to reduce the absorption loss. The proposed resonator is realized using a 0.18- $\mu $ m CMOS process, and operated at 140.13GHz with an electrical size of $\boldsymbol {\lambda _{0}}$ /5.1, where $\boldsymbol {\lambda _{0}}$ is the free space wavelength. Experimental results show that the resonator chip achieves a measured Q-factor of 21.4. This compact design offers a feasible route for miniaturized plasmonic devices using the standard CMOS platforms at terahertz frequencies.
Quantitative analysis of slow traps in gallium nitride (GaN) devices remains challenging because many capacitance-based extraction methods rely on an absolute conversion from $C$ – $V$ data to surface potential. In GaN devices, this conversion can be unreliable in the presence of dispersion, nonquasi-static response, leakage, and series/access resistance. In this work, we develop a series-resistance ( ${R} _{\text {s}}\text {)}$ -corrected equivalent-voltage translation (EVT) method for Al2O3/GaN MOS capacitors (MOSCAPs). Instead of reconstructing the absolute surface potential, EVT maps the capacitance transient, after series-resistance correction, onto a premeasured capacitance-voltage reference curve and extracts an equivalent gate-voltage shift. This measurement-based translation yields the time-dependent slow-trap sheet-density change $\Delta $ Nst(t) and an effective time constant from the same transient. For the piranha + SC-1 split, EVT gives $\Delta $ Nst(1 s) $= 1.07\times 10^{{11}}$ ${\mathrm {cm}}^{-{2}}$ after 60 s filling at 4.8 V. This value is close to the hysteresis-based consistency check of $1.12\times 10^{{11}}$ ${\mathrm {cm}}^{-{2}}$ and higher than the value obtained from a surface-potential (SP)-based benchmark on the same corrected dataset. Under an identical transient protocol, EVT also captures the effect of substrate pre-clean, with $\Delta $ Nst(1 s) increasing to $2.07\times 10^{{11}}$ ${\mathrm {cm}}^{-{2}}$ for the HCl split. These results support EVT as a matched-frequency, measurement-based framework for quantitative slow-trap benchmarking and standardized process screening in Al2O3/GaN gate stacks.
To meet the demands for miniaturization, lightweight, and fast transient response operation of S-band 3-MW multibeam klystrons (MBKs) in medical accelerator applications such as FLASH radiotherapy, a novel high-efficiency S-band 3-MW MBK is proposed in this article. The design employs a frequency-tuned gain cavity technique in the RF circuit to extend bandwidth, along with an ultracompact periodic reverse permanent magnet (PRPM) focusing system and locally trenched beam tunnels to enhance beam transmission. Theoretical analysis indicates that, at 2.998 GHz, the MBK achieves a pulsed output power of 3.7 MW with an RF conversion efficiency of 55.9%. The 3-dB power bandwidth under constant RF input drive exceeds 50 MHz, while the overall dimensions are as compact as $0.2\times 0.75$ m. A prototype of the proposed S-band MBK has been fabricated and experimentally verified. Hot-test results at 2.998 GHz show a DC beam transmission of 88% and a dynamic beam transmission of 82%. The measured pulsed output power reaches 3.7 MW, and the 3-dB bandwidth under constant RF drive is 45 MHz, which is about two times that of existing peers. In addition, the tube weight, including the focusing system, is about 45 kg. The experimental results agree well with theoretical predictions under comparable transmission conditions. These studies demonstrate the significant potential of the proposed compact, lightweight, and broadband S-band 3-MW MBK for future accelerator applications.
To improve the microwave performance of the capacitive microelectromechanical system (MEMS) microwave power detection chips and more comprehensively investigate the thermal–mechanical coupling effect during the beam vibration, a novel MEMS microwave power detection chip based on double fixed beams is designed in our previous work. The thermoelastic effect is considered. Two types of damping, namely air damping and thermoelastic damping, are integrated to explore the impact of the beam on the performance of the chip. On this basis, the chip’s sensitivity and overload power are analyzed. A lumped circuit model is built to study the microwave characteristics of the chip. The measured results show that within the range of 8–10 GHz, the values of return loss remain below −10 dB, demonstrating great microwave characteristics. The sensitivity of the MEMS microwave power detection chip based on double fixed beams is 14.42fF/W@10 GHz within 200-mW input power, while the theoretical value of sensitivity is 14.65 fF/W, with a relative error of only 1.59%. Compared to traditional theoretical models of classical mechanics, the inclusion of thermal–mechanical coupling effect in this work has improved the prediction accuracy by over 20%. These results demonstrate that the analysis of the thermal–mechanical coupling effect provides significant theoretical support for the design of MEMS microwave power detection chips.
Carbon nanotube field effect transistors (CNT FETs) are highly susceptible to gate bias stress, which poses significant challenges to their operational stability and reliability. In this study, systematic characterizations were performed to investigate and compare the degradation behaviors of bottom-gated, aligned CNT FETs under positive and negative gate bias stress (PGBS and NGBS). Transfer characteristics were dynamically monitored throughout the stress application and subsequent recovery phases, and a quantitative fitting analysis was conducted using the stretched-exponential function to extract threshold voltage drift parameters. The results indicate that PGBS induces a positive threshold voltage drift that is fully recoverable, whereas NGBS leads to a negative threshold voltage drift that exhibits incomplete recovery. The stretching exponent $\beta $ remains close to 0.5 during stress for both bias types, while diverging during recovery, increasing for PGBS and decreasing for NGBS, reflecting distinct degradation characteristics under the two stress conditions. This stress-dependent behavioral discrepancy was further validated through cyclic gate bias stress tests, confirming the repeatability and reproducibility of the observed stress-response behaviors. Furthermore, current transient measurements and the derived time constant spectra were employed to characterize the evolution of distinct traps. Measurements reveal that both water-related traps at the CNT/SiO2 interface and oxide traps within the dielectric layer exhibit opposite variation trends between the stress application and subsequent recovery phases. By correlating the evolution of these traps with variations in device electrical performance, we confirm that the physical mechanism governing the device’s degradation and recovery dynamics under gate bias stress involves reversible redox reactions at the CNT/SiO2 interface, coupled with proton migration into and out of the SiO2 dielectric layer.
This work investigates the leakage mechanisms of nonetched-barrier (NEB) metal–oxide– semiconductor (MOS)-gated edge termination (GET) AlGaN/gallium nitride (GaN) Schottky barrier diodes (SBDs). By employing an etch-free architecture, the device achieves breakdown voltages (BVs) of 1168and 2030V at anode-to-cathode spacings (Lac) of 13and $18~\mu $ m, respectively. Temperature-dependent reverse $I$ – $V$ measurements and Arrhenius analysis reveal that the dominant leakage mechanism differs between the recessed-anode (RA) and NEB architectures, transitioning from field-enhanced tunneling to trap-assisted thermal emission. At high reverse bias, the leakage current exhibits buffer-limited characteristics, consistent with the extracted activation energy and the observed breakdown behavior. Pulsed $I$ – $V$ characteristics further confirm the improved interface quality and the effective suppression of shallow surface-related leakage paths. As a result, the NEB-SBD exhibits a reduction in reverse leakage current by nearly three orders of magnitude compared to an RA reference SBD. In addition, multifinger devices demonstrate the scalability of the proposed architecture, indicating its potential for high-voltage GaN power SBD applications.
