Lossless data compression is highly desirable in enterprise and cloud environments for storage and memory cost savings and improved utilization I/O and network. While the value provided by compression is recognized, its application in practice is often limited because it's a processor intensive operation resulting low throughput and high elapsed time for compression intense workloads.The IBM POWER9 and IBM z15 systems overcome the shortcomings of existing approaches by including a novel on-chip integrated data compression accelerator. The accelerator reduces processor cycles, I/O traffic, memory and storage footprint of many applications practically with zero hardware cost. The accelerator also eliminates the cost and I/O slots that would have been necessary with FPGA/ASIC based compression adapters. On the POWER9 chip, a single accelerator uses less than 0.5% of the processor chip area, but provides a 388x speedup factor over the zlib compression software running on a general-purpose core and provides a 13x speedup factor over the entire chip of cores. On a POWER9 system, the accelerators provide an end-to-end 23% speedup to Apache Spark TPC-DS workload compared to the software baseline. The z15 chip doubles the compression rate of POWER9 resulting in even much higher speedup factors over the compression software running on general-purpose cores. On a maximally configured z15 system topology, on-chip compression accelerators provide up to 280 GB/s data compression rate, the highest in the industry. Overall, the on-chip accelerators significantly advance the state of the art in terms of area, throughput, latency, compression ratio, reduced processor utilization, power/energy efficiency, and integration into the system stack.This paper describes the architecture, and novel elements of the POWER9 and z15 compression/decompression accelerators with emphasis on trade-offs that made the on-chip implementation possible.

High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs 15 Glenn Henry (Centaur Technology), Parviz Palangpour (Centaur Technology), Michael Thomson (Centaur Technology), J Scott Gardner (Advantage Engineering LLC), Bryce Arden (Centaur Technology), Jim Donahue (Centaur Technology), Kimble Houck (Centaur Technology), Jonathan Johnson (Centaur Technology), Kyle O'Brien (Centaur Technology), Scott Petersen (Centaur Technology), Benjamin Seroussi (Centaur Technology), and Tyler Walker (Centaur Technology)

The IBM 3081 represents an important step in the evolution of large-scale data processing systems. The incorporation of LSI technology in its design has resulted in a departure from the use of traditional support tools and techniques. Its increased processing capabilities and its dyadic organization have further accented the requirements for high availability and ease of operation. This paper describes the Processor Controller unit of the 3081 Processor Complex, which handles the functions of maintenance, monitoring, and control of the system. It discusses how this unit has dealt with these changes to keep pace with the demands of advanced technology and improved system availability. In providing the necessary test and support functions of reset and manual control, the Processor Controller exploits the level-sensitive scan design capability of the 3081 to obtain read/write access to all latches and arrays. This design approach, coupled with significantly expanded capabilities for error recovery, configuration control, and diagnostics, has significantly affected the structure and capabilities of the Processor Controller.