A new yield loss mechanism is described that is related to the etching of Cu in deionized water. Water that contains high concentrations of dissolved oxygen can etch Cu at the bottom of vias during pre-metallization wet cleans. The etching creates voids in the Cu which remain after metallization, resulting in high resistance and functional fails in the affected array circuits. The dissolved oxygen concentration in the deionized water must be minimized to prevent etching of Cu.

Crystalline defects are observed on the surface of fluorosilicate glass (FSG) dielectrics after prolonged storage in air. The crystals have a hexagonal morphology and contain NH3 and F, suggesting that they consist of NH4F. Metal maze yields are not affected by the crystals, even though the crystals are present in trenches. However, via resistance and continuity are severely degraded by the crystals, unless a clean is used prior to metallization.

This paper discusses the integration of damascene copper in hybrid dielectrics. The hybrid process employed PECVD FSG (K=3.6) for vias and SiLK(TM) (K=2.6) with a SiC (K=4.5) hard mask for wires. Key integration issues included wire/via height control and variability, hard mask integration, via resistance variability, electromigration (EM) lifetime, stress migration (SM) lifetime, thermal cycling (TC) reliability, and wiring defect density. Hybrid processing considerably reduced the wire sheet resistance variability as compared to SiLK(TM)- or FSG-based wiring. EM lifetime was comparable to previously reported data [1-2]; and no stress migration or thermal cycling fails occurred in any test-sites. The hybrid FSG-SiLK(TM)-based wiring had similar to20% lower wire RC delay as compared to FSG-based wiring.

The integration of Cu with low-k dielectrics poses a number of challenges. In this paper, we describe yield issues associated with integration of three different low-k dielectrics; FSG (fluorosilicate glass), OSG (organosilicate glass), and polymers. Process issues that are discussed include patterning of the dielectrics, cleaning of the Cu surface, and Cu polishing.

After determining the technology requirements required to service the integrated circuit design community, a process technology must be demonstrated to be manufacturable. Often a process must be installed and qualified on multiple manufacturing lines and extended to a broader class of designs and tools than originally envisioned. This may accomplished through properly designed business processes and through adroit and effective empirical demonstrations.

Integration of Cu/SiLK dual damascene interconnects and aspects of their reliability are discussed. The basic integration scheme employs a multilayer hardmask in order to facilitate photolithographic reworkability. Process details within the hardmask integration scheme can have a strong influence on dielectric and metal reliability. Examples of how electromigration resistance, thermal cycle stability, stress migration stability, and time dependent dielectric breakdown depend on several process parameters are given.

Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 /spl mu/m CMOS products later this year. Features of this technology are presented here, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data is presented from this testing, ranging from experiments designed to promote copper contamination of the MOS devices, to functional stressing of packaged SRAM modules. A fully-functional high-performance microprocessor with 6 levels of Cu wiring has also been demonstrated. The results in all areas are equal to or better than standards set by our current Al(Cu) wiring technology. This work demonstrates that the potential problems associated with copper wiring can be overcome to produce reliable and properly-functioning ULSI CMOS chips with a cost-effective, extendible process.

We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl mu/m, on a fully-scaled sub 0.25 /spl mu/m, 1.8 V CMOS technology. The Cu wiring has advantages of significantly lower resistance, higher allowed current density, and increased scalability, relative to comparable Ti/Al(Cu) wiring. These benefits in turn have enabled the scaling of pitch and thickness, from reduced-capacitance, high-density lower levels to low RC global wiring levels, consistent with high-performance and high-density needs. The integrated Cu hardware was evaluated according to a comprehensive set of yield, reliability, and stress tests. This included fully functional, high-density 288 K SRAM chips which were packaged into product modules and successfully tested for reliability. Overall, we find the results for full Cu wiring meet or exceed the standards set by our Al(Cu)/W-stud technology.

The role of the wafer substrate in processing of chemically amplified DUV photoresists has been examined. Various substrates including silicon, oxide, titanium nitride, silicon nitride and metals were investigated with both positive and negative tone DUV resist systems. A `substrate contamination' effect was observed in some cases, which results in distorted photoresist profiles at the substrate/resist interface. This effect is interpreted in terms of neutralization of the photogenerated acid in the resist, and is dependent upon substrate deposition and clean conditions as well as exposure and post-expose bake processing. In addition, organic antireflective films are seen to act as effective barrier layers in some cases.