This paper presents the factors that an Augmented Reality (AR) application designer must look at whilst implementing AR applications on mobile platforms. There are certain implementation and design issues that are critical to the success of an AR application. The trigger response time (TRT) and mobile platform battery consumption are the two main parameters that are looked at in the research preseted. The test application was designed using a combination of Vuforia, Unity and Blender platforms, and the mobile platform used was an Android based One Plus 3T phone. The results discuss the impact of trigger image complexity, 3d object complexity and ambient light on the response time and battery life.

This paper focuses on the implementation of a modified lightweight version of the MODBUS protocol optimized for wireless sensor networks. Here, the master and slave arrangement is made wireless using low cost and multi-featured RF modules (nRF24L01P). The modified MODBUS Packet Data Unit is sent in the data frame of the nRF24L01P. As part of the implementation in this paper the nRF24L01P's feature of “Enhanced ShockBurst” is utilized for auto acknowledgement of the received data which increases the system reliability. Also, a power saving feature is embedded in the slave modules to reduce the overall power consumption. A practical approach is taken to measure the total battery life of the device and the overall speed of the system.

This paper explores the use of On-chip cryptographic units for implementing security in low cost wireless sensor networks. The objective of this research is to reduce the deployment time and computational complexity of security protocols in WSNs, whilst keeping security related performance parameters at par with the current state-of-the-art. A method is proposed to continue using simple radio transreceiver for communication while ensuring that the information contained therein is sufficiently secure, without increasing processing time significantly. An off-the-shelf SoC (NXP MK64Fx series) with an on-chip memory mapped cryptographic unit is used as a test platform. The results demonstrate that without any loss in security parameters like key space and adversary's advantage, we are still able to achieve a low cost and low complexity solution. We have shown that the core protocol stacks of simple radio transreceivers can be made secure without significantly increasing processing time in the system. Such an approach provides greater flexibility in controlling the security parameters while allowing for greater optimization of the system.

Securing digital data is a current need of the hour. Increasing computational power makes brute force attacks on cryptographic systems a feasible attack, requiring higher key length to protect data. On the other hand, concealing data using steganographic techniques always leaves a trace. Hence embedding of data directly in steganography is not secure as the system is only secure until the concealment is not discovered. A hybrid solution to the problem is proposed in this paper, where cryptographic functions are incorporated in the embedding process of steganography. Using chaotic transforms to randomize the data, as well as the data embedding process makes the embedded information nearly indistinguishable from noise.

Passive Keyless Entry (PKE) systems have embarked to define the market of basic security systems. Low power consumption and maximum data privacy are two parameters that make these setups deployable. With the Bluetooth protocol being enabled with smarter processing and lower energy consumption to create the Bluetooth Low Energy (BLE) segment of peripherals, the focus of this research is to investigate keyless entry systems using this technology. The system has been prototyped using the Programmable System on Chip (PSoC-4 BLE) from Cypress Semiconductors with a BLE peripheral as the host and the user smartphone as the client. The user will advertise through the smartphone BLE and a predefined whitelist at the client end decides which host is granted access. Development was concentrated on taking maximum advantage of the power saving modes available in BLE. There were a considerable number of design issues and tradeoffs that needed to be considered were and looked into. Design issues and tradeoffs between parameters such as optimal scan duty cycle, scan range, power consumption and minimum authentication time have been discussed with implementation results.

Tracking of objects from a video stream is a current research challenge with widespread applications. This paper explores an approach that deals with efficient object tracking in both two dimension as well as stereo setups. It deals with real time situation involving environmental conditions, and also handling occlusion in both 2D and 3D environments. This below provides a novel way to aid in object tracking with a stereo camera pair as well as a single camera.

Multifunction image processing systems are typically deployed at the application site, but with the advent of Internet of Things(IoT) the design of such systems that are accessible remotely by applications over the internet is the need of the hour. These systems, being designed for data heavy applications need to possess a novel architecture design for image filtering and processing. This paper presents a multi-function image processing system that is accessible over the internet and is prototyped using a System on Chip (SoC) and FPGA interface. A pipelined based approach, inspired by a shift register based Random Access Memory design has been implemented for on-the-fly computation and minimal use of on-chip resources. The realization of the system was done using a low cost Spartan 6 FPGA and a Raspberry-pi B+ representing the ARM cortex based SoC. Data transfer between the FPGA and SoC has been achieved using a UART protocol. Computation time of different frame sizes for the system and standard I.P. software tools have been documented. Chip utilization and delays have also been reported.

An efficient modeling of motor drivers using an H Bridge configuration driven by charge pumps controlled by embedded components is presented. N-channel MOSFETs and charge pumps together eliminate the problems of Dead time of MOSFETs and High values of RDS (ON). The embedded system using an ATMEL microcontroller drives the load and monitors the load voltages and input PWM to establish a closed loop system by comparing it with the stored threshold state space parameters of the motor, also in turn preventing MOSFET damage by synchronized control over the gates. Charge pump readings have been reported along with feedback readings for the microcontroller. Results obtained are in range with expected outputs.

Multifunction parallel image processing systems use standard buses to do inter core communication. Faster and scalable approaches are needed to improve the throughput of the system, but for data heavy applications like Image Processing (IP) algorithms there is a need for constant data transfer between different functional blocks on chip. The solution would either be hardwired buses or controlled communication. Networks-On-Chip (NoC) present a systematic solution, and can succeed a hardwired bus solution in a scalable form. This paper presents a multifunction image processing system prototyped on a single reconfigurable platform. The different IP cores have been implemented keeping in mind on-the-fly processing times and frame rates. The different modules are interconnected using a Torus architecture NoC with an information heavy packet structure and capable of addressing multiple nodes simultaneously. The implementation was done using a low cost Spartan 6 FPGA. Frame rates for standard sizes and chip utilization has been reported.

The use of chaos for image encryption over traditional text based encryption methods has gained momentum due to its superior performance. In this paper, a fast encryption method is presented which utilizes a substitution-permutation network using two chaotic maps. Logistic maps are used to create substitution box while key dependent rectangular chaotic maps is used for permutation of pixels. The algorithm is applicable to images of any dimension. It shows improved performance and a good level of security.

This paper proposes an architecture that uses the ultra-low power Bluetooth Low Energy (BLE) wireless standard and a hybrid topology to reduce power consumption in IOT based wireless sensor networks (IOTWSN). A lot of work has been done in the field of Wireless Sensor Networks (WSN) in recent years. Efforts to make efficient, low cost, scalable and easily deployable WSN have been on going. In order to reduce cost and improve life of a sensor node, it is necessary to optimize battery usage and power consumption. This paper looks at BLE as a potential candidate to reduce power in IOTWSN. BLE based activity detection is also incorporated into the system to avoid power wastage in real-time monitoring. The power consideration of the proposed architecture is compared to existing wireless technologies used in WSN.

This paper describes the implementation of a cloud based Xilinx ISE platform that can be used by the users remotely. The Remote Xilinx environment is used to provide remote access to the Xilinx Integrated Software Environment (ISE). The main aim of the research presented is to highlight how users can access FPGA design resources from anywhere in combination with a potential remote FPGA lab. The architecture of the cloud based platform is described with a load analysis for the server. The cloud based approach has been proposed and a comparative analysis is discussed based on the results obtained. The remote environment is developed on the Ubuntu (open source) operating system by using Python and Hypertext Preprocessor (PHP) scripting languages. The open source Apache server is used for running Xilinx environment on a server and open source analysis tools are used to perform server load analysis for running Xilinx environment on the server system.

Digital video is one of the most popular multimedia data exchanged over the internet. Previous cryptography studies have focused on text data. The encryption algorithms developed for text data may not be suitable to multimedia applications because of large sizes of video. Analgorithm is proposed in which a video file is encrypted by considering each frame a colour image. Each video is broken down into its constituent frames. Chaotic mapping algorithms are applied on all the frames and in the temporal domain of the video as well. The algorithm was run on different videos, and results were obtained show improved performance time and good security. Initial comparison against existing methods also shows that encryption time required is less, while recovered plaintext also has fewer distortions.

This paper discusses a FPGA-PSOC interface to be used as a lab platform in engineering education. We selected the Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) in the Programmable System on Chip (PSoC) device to externally interface with a Spartan 3E FPGA. Implementation on the FPGA was done using VHDL while analysis and experiments were performed to test for accuracy and speed. Results show that there was promise in using the interface and combination of the two devices for future teaching platforms with errors found to be sub 8% in both the ADC and DAC interfaces.

A first-order neuromorphic implementation of structural plasticity is shown. Our circuit models spiking behavior of somatosensory neurons and neuronal receptive fields in the upper layers of the rodent barrel (somatosensory) cortex while replicating biological observations of experience-dependent changes in receptive field organization, network topology and synaptic connectivity in silico. Anatomical changes in synaptic connectivity have been modeled using analog switching, based on changes in neural activity. We demonstrate the effects of loss of inhibition and sensory (whisker) inputs with our circuits.

A CMOS neuromorphic circuit is proposed with two main features. First, we emulate the uptake of neurotransmitters by astrocytes, a type of glial cell, that plays an active role in the coordination of information between neurons. Second, we propose a synapse inactivation mechanism, which prevents the saturation of postsynaptic neurons in the absence of an astrocytic process. We show the influence of both mechanisms on the firing of a small network of neurons interacting with an astrocyte. We also incorporate the release of gliotransmitters by the astrocytic microdomain into this network according to the activities of neighbor synapses. This work contribute to better understanding the importance of astrocytes in neuro-glia interactions, and illustrates the active role astrocytes play.

A biomimetic carbon nanotube synapse, the portion of the neuron that receives inputs from other neurons, has been fabricated in the laboratory as an analog circuit. The waveforms input to the synapse and output from the synapse resemble biological waveforms in shape and relative amplitudes and durations. This working circuit is an important first step towards the use of nanotechnology for biomimetic neural circuits and neural prosthesis.

Glial cells play an active role in the central nervous system. We present a CMOS neuromorphic circuit as part of the BioRC Biomimetic Real-time Cortex that emulates a glial microdomain, including several neurons interconnected in a small network. The glial cell, an astrocyte, influences neural behavior to stimulate a neuron to fire. Without glial intervention, the neuron would not have sufficient excitatory postsynaptic potential to fire. This circuit represents a first-order model of the reciprocal feedback between neurons and astrocytes involving gliotransmitters and neurotransmitters, and of the calcium concentrations induced in the astrocytes. Much more complex interaction has been observed and will be implemented in the future.

Starburst Amacrine Cells (SACs) play a major role in the detection of directional motion in the biological retina. The starburst amacrine cell has intrinsic electrical mechanisms for producing directional selectivity (DS). GABA transmitter-receptor interactions between two overlapping SACs make DS more robust. We present a compartmentalized CMOS neuro-morphic circuit that models a portion of two biological starburst amacrine cells in the retina and includes a simplified model of reciprocal interaction between the dendritic branches of SACs. We demonstrate that a neuromorphic circuit incorporating the reciprocal synapses enhances the responses in the neuromorphic dendritic tip and generates robust directional selectivity.