The metal-ferroelectric-insulator-semiconductor (MFIS) structure using a SrBi2Ta2O9 (SBT) film as a ferroelectric layer and a lanthanum dysprosium oxide (LDO) film as an insulating buffer layer was prepared. The LDO thin film and the SBT film were deposited by using the sol-gel method. The sol-gel-derived LDO thin films on Si had very flat and smooth surface morphologies. The equivalent oxide thickness (EOT) values were about 10.1 nm, 12.5 nm, and 12.8 nm for 750 degrees C, 800 degrees C, and 850 degrees C, respectively. Also, the relative dielectric constants of the 750 degrees C-annealed, 800 degrees C-annealed and 850 degrees C-annealed LDO films were about 15.4, 12.5, and 12.2, respectively. On the whole, the leakage current densities showed good characteristics regardless of the annealing temperature. Especially, the leakage current property of the 850 degrees C-annealed LDO film was visibly superior to those of the others at voltages over 6 V. The C-V characteristics of the Au/SBT/LDO/Si structure showed clockwise hysteresis loops, and the memory window width increased as the bias voltage was increased. Also, the leakage current density was lower than 5 x 10(-7) A/cm(2).

To fabricate a metal-ferroelectric-insulator-semiconductor (MFIS) structure, we prepared a (Bi,La)(4)Ti3O12 (BLT) film as a ferroelectric layer and a dysprosium-zirconium-oxide (DZO) thin film as an insulating buffer layer on a p-type Si (100) wafer by using a sol-gel method. Equivalent oxide thickness (EOT) values of the DZO thin films deposited on Si were about 12.4 nm, 11.9 nm, 11.2 nm, and 11.1 nm for 650 degrees C, 700 degrees C, 750 degrees C, and 800 degrees C, respectively. The leakage current densities showed good characteristics, regardless of annealing temperature variations. In case of the 750 degrees C-annealed DZO thin film, a negligible hysteresis width (Delta V-FB) was observed. The capacitance-voltage (C-V) characteristics of the 300-nm-thick BLT film on the 750 degrees C-annealed DZO/Si structure showed clockwise hysteresis loops, and the memory window width increased as the bias sweep voltage increased. The maximum value of the memory window width was about 1.9 V at a bias sweep voltage of +/- 7 V, and the leakage current density was lower than 5 x 10(-7) A/cm(2) at 5 V.

We fabricated the n-channel metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) using an Au/(Bi,La) 4 Ti 3 O 12 /LaZrO x /Si(100) gate structure. We observed that the LaZrO x thin film had the equivalent oxide thickness value of around 8.7 nm. The 420-nm-thick (Bi,La) 4 Ti 3 O 12 film on a LaZrO x /Si structure, showed a good ferroelectric property and had the width of the memory window of 1.2 V for a bias voltage sweeping of ± 7 V. The drain current-gate voltage (I D -V G ) of an Au/(Bi,La) 4 Ti 3 O 12/ LaZrO x /Si(100) MFIS-FET showed threshold voltage shift (memory window width) owing to the ferroelectric (Bi,La) 4 Ti 3 O 12 film. The drain current-drain voltage (I D -V D ) characteristic curves exhibit typical n-channel field-effect transistor current-voltage characteristic. However, relatively large leakage current observed in the I D –V G and the I D –V D characteristic curves, might be caused by the high density of pores in the BLT film.

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with metal/ferroelectric/semiconductor gate stack (MFS-FETs) have superior advantages such as non-destructive read operation and high density. However, the interfacial reactions between ferroelectric materials and Si substrates make it difficult to obtain good electrical properties of MFS-FETs. As an alternative solution, Fe-FETs with a metal/ferroelectric/insulator/insulator/semiconductor gate stack (MFIS-FETs) have been proposed. We prepared SrBi2Ta2O9 (SBT) film as a ferroelectric layer and LaZrOx (LZO) film as the insulating buffer layer, and then fabricated the n-channel Fe-FETs with the Au/SBT/LZO/Si structure. The thickness of the LZO buffer layer and SBT film deposited by a sol-gel method were about 35 nm and 450 nm, respectively. From the electrical properties of the LZO film on Si, no hysteresis was observed in the C-V curve and the leakage current density was about 1.4 × 10-7 A/cm2 at 5 V. SBT film on the LZO/Si structure was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The C-V characteristics of Au/SBT/LZO/Si structure showed a clockwise hysteresis loop and the memory window width increased as the bias voltage increased. The fabricated Fe-FETs showed typical n-channel MFIS-FETs C-V characteristics and the current on/off ratio was about 103. Also, the memory window width was about 0.7 V.

To obtain a metal–ferroelectric–insulator–semiconductor (MFIS) structure, we fabricated ferroelectric SrBi2Ta2O9 (SBT) film on a p-type Si (100) wafer with a LaZrO x (LZO) buffer layer by means of a sol–gel technique. The sol–gel deposited LZO film according to the different annealing temperatures had a good surface morphology even though the crystalline phase was not an amorphous phase. In particular, the root-mean-squared (RMS) surface roughness of the 750-°C-annealed LZO film was about 0.365 nm and its leakage current density was about 8.2 × 10−7 A/cm2 at 10 V. A Au/SBT/LZO/Si structure with different SBT film was fabricated. The C–V characteristics of the Au/SBT/LZO/Si structure showed a clockwise hysteresis loop. The memory window width increased as the SBT film thickness increased. The 600-nm-thick SBT film was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The memory window width of the 600-nm-thick SBT film was about 1.94 V at the bias sweep voltage ±9 V and the leakage current density was about 6.48 × 10−8 A/cm2 at 10 V.

To investigate the possibility of LaZrOx thin film as a buffer insulator for ferroelectric thin films, we fabricated (Bi,La)(4)Ti3O12 (BLT) ferroelectric films on a silicon substrate by using the LaZrOx buffer insulator in forming the metal-ferroelectric-insulator-semiconductor (MFIS) structure. We prepared the LaZrOx thin film and BLT films by using a sol-gel method. The films were characterized by X-ray diffraction (XRD) analysis, atomic force microscopy (AFM), capacitance-voltage (C-V) characteristics, and leakage current density-voltage (J-V) characteristics for both LaZrOx/Si and BLT/LaZrOx/Si structures. From C-V measurement results, equivalent oxide thickness (EOT) values of LaZrOx thin films annealed at 700 degrees C and 800 degrees C were about 9 nm and 10 nm, respectively. Negligibly small hysteresis loops were observed for both LaZrOx/Si structures. The leakage current density at an applied voltage of 5 V was lower than 1.0 x 10(-7) A/Cm-2 for all samples. For the case of the BLT/LaZrOx/Si structure, we obtained randomly oriented polycrystalline BLT films. From the C-V measurements, clockwise ferroelectric hysteresis loops were observed and the memory window width became larger as the bias voltage sweep increased from +/-3 V to +/-9 V. The memory window width was about 1.0 V for bias voltage sweep of 7 V. The leakage current density was lower than 1.0 x 10(-6) A/cm(2) at 10 V.