As the most scaled memory solution at present, we for the first time developed and begun volume production of 14nm DRAM to extend the continuous shrink trend in semiconductor memory industry. In the new era of 14nm node DRAM and beyond, process integration and device performance are both essential due to the rapid increase of memory cell disturbance and resistance. To resolve the difficulty of process integration, five-layer EUV processes and L-CNT (Line-type storage node contact) scheme were devised, reducing the number of process steps by approximately 20%. To boost device performance, extremely shallow doping engineering played a pioneering role to advance the performance of PMOS transistor by 40% in terms of contact resistance. Our 14nm DRAM will provide the finest and most advanced solution for the next-generation DRAM platform–DDR5 and beyond.

The component of cell parasitic resistance at sub-20nm 4th generation DRAM cell transistor is investigated. To evaluate the cell characteristics, the Gate Buried Contact (GBC) to Active contact formation method with varied dopant concentrations was studied. We have discovered a scalable methodology that simultaneously reduces parasitic resistance and leakage with regard to Gate Induced Drain Leakage (GIDL). Also, we proved the importance of interface quality of Direct Contact on Cell (DCC) in order to reduce the parasitic resistance. The failure analysis is conducted by segmenting the resistance with Test Element Groups (TEGs) at wafer level. And the process windows and local variations from fabricated devices are electrically verified by core failure analysis. Through this investigation, we proposed the scalable methodology that can sustain generational scalability of DRAM.