Varying a supply voltage using a DC-to-DC converter can significantly improve the efficiency of RF power amplifiers (PAs) for low-power RF transceivers. However, intrinsic switching noise from a conventional DC-to-DC converter operating in fixed Pulse-Width Modulation (PWM) can affect the system performance since the spectral components in the switching noise are confined in the fundamental switching frequency and its harmonics. This harmonic noise will have detrimental effects on the performance of the microwatt’s transmitter due to its low output power. Especially for microwatts systems, the minimized size of the inductor will increase the spurious noise due to increased peak-to-peak inductor current. By relocating the spurious noise and reducing peak noise from a switching converter, this paper proposes the technique to prevent high noise spurs in a microwatt transmitter, combining both pseudo-random frequency stepping and monotonic frequency stepping. Both modulation circuits are implemented in CMOS 0.18 µm process and incorporated to achieve the proposed DC-to-DC converter system. The measurement results indicate that the proposed PWM ramp signal modulator with random frequency modulation in a DC-to-DC converter can reduce the peak of the spurious noise-power by 22 dB. Monotonic frequency modulation with various frequency steps reduces the peak of the spurious noise-power by 18 dB.

For a frequency-division duplex (FDD) wide-band code-division multiple-access (WCDMA) system, transmit (TX) signal leakage at the receiver input degrades the receiver performance. To cancel this TX leakage, a frequency selective feedback was previously proposed, but it had an unpredictable feedback loop characteristic due to the uncertainty of the duplexer impedance. This paper presents a new method to achieve TX leakage cancellation regardless of the duplexer impedance. In addition, a local oscillator (LO) phase shift technique is proposed to apply this method for multi-band. A receiver adopting these proposed techniques is implemented using a 0.18-m CMOS process to prove the concept. The measured TX attenuations of the high- and low-band are 17-dB and 20-dB, respectively, and the measured noise Figure (NF) degradations of the high- and low-band are 0.6-dB and 0.5-dB, respectively. The measurement results demonstrate effectiveness of the proposed techniques.

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Since the first demonstration of 60GHz connectivity in 1895 there has been much interest and promise in the future of mmW gigabit wireless technology. It has been only recently, with the emergence of millimeter wave and sub-THz (up to 300GHz) CMOS based technology and its potential for true monolithic single chip integration that one can envision a new class of systems and applications ranging from ultra-high speed data transmission, video distribution, portable radar, sensing, detection and imaging. In this presentation we focus on the layer 1 radio challenges for deployment of mmW links: co-designed CMOS digital radio with efficient power consumption. Approaches are reviewed which address the high capital cost structure (Capex) and the high operational cost structures (Opex) of mmW gigabit link solutions, bits to antenna. We will also review the market pull and requirements for emerging use cases for mmW gigabit connectivity from 5G to IOT.

We present a 1.9-GHz high-power-handling complementary metal-oxide-semiconductor (CMOS) transmit/ receive (T/R) switch with the impedance transformation technique (ITT). The losses of the T/R switch, including matching networks, are analyzed, and the design method for the selection of an optimal switch operating impedance (RSW) is presented. The proposed T/R switch is implemented in a standard 0.18-mu m CMOS process. Experimental data show that the proposed design achieves more than 2 W of power-handling capability.

A detection and compensation technique for LO phase mismatches is presented to reduce noise in the mixer. Based on theoretical analysis and simulation, this work shows that the LO phase mismatch degrades the noise figure, gain, and linearity of the mixer. To compensate the LO phase mismatch, a new concept of the mixer is proposed, and its prototype is fabricated in 0.18-μm CMOS technology. In addition, a current bleeding mixer, which is known for low flicker noise topology, is also fabricated for comparative purposes. From the measured results, the proposed mixer reduces the flicker noise corner frequency by almost half when it is compared to the current bleeding mixer. Moreover, the proposed mixer improves gain and linearity without additional power consumption.

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This brief presents a nonisolated multilevel linear amplifier with nonlinear component (LINC) power amplifier (PA) implemented in a standard 0.18-μm complementary metal-oxide- semiconductor process. Using a nonisolated power combiner, the overall power efficiency is increased by reducing the wasted power at the combined out-phased signal; however, the efficiency at low power still needs to be improved. To further improve the efficiency of the low-power (LP) mode, we propose a multiple-output power-level LINC PA, with load modulation implemented by switches. In addition, analysis of the proposed design on the system level as well as the circuit level was performed to optimize its performance. The measurement results demonstrate that the proposed technique maintains more than 45% power-added efficiency (PAE) for peak power at 21 dB for the high-power mode and 17 dBm for the LP mode at 600 MHz. The PAE for a 6-dB peak-to-average ratio orthogonal frequency-division multiplexing modulated signal is higher than 24% PAE in both power modes. To the authors' knowledge, the proposed output-phasing PA is the first implemented multilevel LINC PA that uses quarter-wave lines without multiple power supply sources.

In this paper, we present a 1.9 GHz CMOS transmit/receive switch with the common mode shunt configuration and adaptive deep N-well (DNW) biasing techniques in order to achieve a high port-to-port isolation. The common mode shunt structure provides a low impedance shunt path to suppress the leakage in the off-switching state, and adaptive DNW biasing can cancel leakage from differential signals in the substrate. Experimental data shows that the proposed design achieves up to 8–10 dB higher port-to-port isolation than that of a conventional switch topology while maintaining insertion loss and power handling capability. The proposed switch is implemented in a standard 0.18-µm CMOS process and compared with the reference design in the TX and RX mode.

Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-mu m CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.