Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalog as well as to use machine learning techniques to score and filter patterns to identify which ones are critical. In this paper, data mined from a library of scored patterns from established designs is applied to the analysis of diagnosis results from a new design to improve defect root cause analysis (RCA). The flow for this approach is as follows: patterns interacting with nets reported in diagnosis callouts are selected as patterns of interest (POIs) from the catalog of all patterns. Next, features of interest (FOIs) are extracted from all POIs to build a dataframe. Finally, volume diagnosis results identifying nets with likely open or short defects are added to the dataframe. RCA is performed using the dataframe to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis. The approach described above is applied to products in high-volume manufacturing using a leading-edge technology node. Silicon validation results will be included for example applications.

Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.

Fiber reinforced polymer (FRP) composites featuring outstanding fatigue performance, high specific stiffness and strength, and low density have evolved as critical structural materials in aerospace applications. Microscale damage such as fiber breakage, matrix cracking, and delamination could occur in layered composites compromising structural integrity, emphasizing the critical need to monitor structural health. Early damage detection would lead to enhanced reliability, lifetime, and performance while minimizing maintenance time, leading to enormous scientific and technical interest in realizing physically stable, quick responding, and cost effective strain sensing materials, devices, and techniques with high sensitivity over a broad range of the practical strain spectrum. Today's most commonly used strain sensing techniques are metal foil strain gauges and optical fiber sensors. Metal foil gauges offer high stability and cost-effectiveness but can only be surface-mounted and have a low gauge factor. Optical fibers require expensive instrumentation, are mostly insensitive to cracks parallel to the fiber orientation and may lead to crack initiation as the diameter is larger than that of the reinforcement fibers. Carbon nanotubes (CNTs) have attracted much attention due to high aspect ratio and superior electrical, thermal, and mechanical properties. CNTs embedded in layered composites have improved performance. A variety of CNT architectures and configurations have shown improved piezoresistive behavior and stability for sensing applications. However, scaling up and commercialization remain serious challenges. The current study investigates a simple, cost effective and repeatable technique for highly sensitive, stable, linear and repeatable strain sensing for damage detection by integrating CNT laminates into composites.

Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk are then mapped to functionally equivalent patterns with lower risk. The higher risk patterns are then replaced in the design with their lower risk equivalents. The pattern selection and replacement is fully automated and suitable for use for full-chip designs. Results from 14nm product designs show that the approach can identify and replace risk patterns with quantifiable positive impact on the risk score distribution after replacement.

Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with respect to previous generations is made. In addition to identifying topological patterns that are unique to a particular design, novel techniques are proposed for scoring those patterns based on potential yield risk factors to find patterns that pose the highest risk.

In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measure design changes and the degree of layout regularization. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze.

In this paper, we introduce a fast and reasonably accurate methodology to determine patterning difficulty based on the fundamentals of optical image processing techniques to analyze the frequency content of design shapes which determines patterning difficulties via a computational patterning transfer function. In addition, with the help of Monte- Carlo random pattern generator, we use this flow to identify a set of difficult patterns that can be used to evaluate the design ease-of-manufacturability via a scoring methodology as well as to help with the optimization phases of post-tape out flows. This flow offers the combined merits of scoring-based criteria and model-based approach for early designs. The value of this approach is that it provides designers with early prediction of potential problems even before the rigorous model-based DFM kits are developed. Moreover, the flow establishes a bi-directional platform for interaction between the design and the manufacturing communities based on geometrical patterns.

Pattern matching tools have become increasingly common in physical design flows for verification and layout analysis. Recently developed topological-based pattern matching engines offer several advantages over conventional three-value logic implementations. In this paper the use of such topological engines is explored for measuring physical design regularity, driving improvements in overall regularity, and for implementing targeted enhancements for suboptimal layout configurations.

Design for manufacturability (DFM) has become a key enabler of integrated circuit (IC) production over the past decade. In this paper a comprehensive DFM program for IC designs at the 28nm node and beyond is described from the perspective of a fabless design company. Challenges for future technology nodes are also explored.

In order to extend the optical lithography into sub-72 nm pitch regime, spacer defined double patterning as a self-aligning process option was investigated. In the sidewall defined spacer process, spacer material was deposited directly on the resist to achieve process simplification and cost effectiveness. For the spacer defined double patterning, core mandrel CD uniformity is proven to be a main contributor to pitch-walking and defined a new lithographic process window. Here, the aerial image log-slope is shown to be a measurable predictor of CD uniformity and sidewall angle of the resist pattern. Through resist screening and illumination optimization, resist core-mandrel of 2.5 nm CD uniformity across a focus range more than 200 nm with ± 3.5 % exposure latitude was developed having sidewall control close to the normal. Finally etch revealed that pitch-walking post pitch split can be suppressed below 2 nm within ± 2.5 % exposure latitude.

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options, and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

In this work, we present a novel application of layout printability verification (LPV) to assess the scalability of physical layout components from 32 nm to 28 and 22 nm with respect to process variability metrics. Starting from the description of a mature LPV flow, the paper illustrates the core methodology for deriving a metric for design scalability. The functional dependency between the scalability metric and the scaling factor can then be modeled to study the scaling robustness of a set of representative layouts. Conversely, quantitative data on scalability limits can be used to determine which design rules can be pushed and which must be relaxed in the transition from 32 to 22 nm.