Augmented reality (AR) technologies that enable the overlay of digital information on the real world are widely anticipated to be the next wave of computing platforms. For a truly immersive AR experience, the AR glasses should be lightweight, comfortable, stylish, socially acceptable, and efficient that can be worn all day. Traditional optical devices are very bulky and are not suitable for head mounted displays (HMDs) for AR glasses. Hence, there is an increasing interest in developing nano-optics based devices that are significantly smaller and lighter than the conventional devices. Materials innovation is one of the key pillars that could enable the fabrication of such lightweight devices. In this talk, the impact of new materials like highly transparent, high refractive index (HRI) substrates, litho and patterning materials for device fabrication and permanent optical materials to develop all-day wearable AR glasses will be discussed.

Over the past half-century, the information revolution has brought us from large corporate computational mainframes to the pervasiveness of mobiles in our lives. Many consider augmented reality to be the next leap in this evolution. Fundamentally, it will transform all aspects of our lives enabled by new interface modalities in sight, sound, and touch. The first step to bringing augmented reality to life is creating a great display. In this talk we will discuss Augmented Reality display architecture and the technologies behind various components.

The pursuit of reduced parasitic junction capacitance led to the development of silicon-on-insulator device technology in the 1990s. Planarization technology prior to interconnect metallization had been explored early in the semiconductor industry, relying on reflow of doped glass dielectric. A transition from dimensional scaling with a single level of complementary metal–oxide–semiconductor devices may come to an end. Examples of "cleverness'' in device architecture and process technology are found in abundance throughout the history of the semiconductor industry. Taking a holistic approach to patterning process development in view of device process technology and circuit design has become a new frontier in enabling device scaling. Source mask optimization technology leverages pixelated illumination and co-optimized masks to improve design space coverage and patterning process window on wafer. Pulsed plasma technology has also been explored to enhance etch selectivity by achieving a finer degree of control of the ion energies and chemical species present in the plasma.

We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing. (C) 2017 Society of Photo-Optical Instrumentation Engineers (SPIE)

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Directed self-assembly (DSA) with block-copolymers (BCP) is a promising lithography extension technique to scale below 30nm pitch with 193i lithography. Continued scaling toward 20nm pitch or below will require material system improvements from PS-b-PMMA. Pattern quality for DSA features, such as line edge roughness (LER), line width roughness (LWR), size uniformity, and placement, is key to DSA manufacturability. In this work, we demonstrate finFET devices fabricated with DSA-patterned fins and compare several BCP systems for continued pitch scaling. Organic-organic high chi BCPs at 24nm and 21nm pitches show improved low to mid-frequency LER/LWR after pattern transfer.

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

The utilization of EUV pellicles as protective layers for EUV masks requires the use of refractory materials that can tolerate large temperature excursions due to the non-negligible absorption of EUV radiation during exposure. Additionally, the mechanical stress induced on the EUV pellicle by the thermal load is dependent on the thermal expansion of the material which can be responsible for transient wrinkling. In this study, an ultrathin (20 nm), free-standing membrane based on silicon nitride is utilized as a learning vehicle to understand the material requirements of EUV pellicles under dynamic exposure conditions that are typical of commercial EUV scanners. First, the nanoscale radiative properties (emissivity) and thermo-mechanical failure temperature of the dielectric film under vacuum conditions are experimentally investigated utilizing a pulsed ArF (193 nm) probing laser. The silicon nitride membrane is found to be marginally compatible with an equivalent 80W EUV source power under steady state illumination conditions. Next, the thermal behavior of the EUV pellicle under dynamic exposure conditions is simulated using a finite element solver. The transient temperature profile and stress distribution across the membrane under stationary state conditions are extracted for an equivalent 60W EUV power source and the pellicle wrinkling due to heating and consequent impact on CD uniformity is estimated. The present work provides a generalized methodology to anticipate the thermal response of a EUV pellicle under realistic exposure conditions.

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.In this paper, DSA of lamella-forming BCP was evaluated as a candidate for forming SAV, which requires the DSA process to support structures from circular via to lines and spaces. The basic process flow is similar to general graphoepitaxy method as shown in Fig. 1 (lower). The morphologies of the DSA vias derived from lamellar BCPs were found to be less sensitive to the BCP coating thickness compared to the cylindrical BCP system of similar L0, as reported by Liu et al. This implies that lamellar BCP may provide a larger process window and higher tolerance for local pattern density variation. The profile and the thickness of the residual PS layer of DSA structures were studied using Monte Carlo simulation and FIB cross-section SEM. Furthermore, a series of defectivity study using the lamellar system will be discussed, including film stack, DSA, and etch process fine-tuning. Structural and electrical demo using DSA of lamellar BCP and SAV process will be presented. Finally, the benefits and challenges of implementing DSA for 7nm via process will be discusses.

The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.

In this paper, we discuss the lithographic qualification of high transmission (High T) mask for Via and contact hole applications in 10nm node and beyond. First, the simulated MEEF and depth of focus (DoF) data are compared between the 6% and High T attnPSM masks with the transmission of High T mask blank varying from 12% to 20%. The 12% High T blank shows significantly better MEEF and larger DoF than those of 6% attnPSM mask blank, which are consistent with our wafer data. However, the simulations show no obvious advantage in MEEF and DoF when the blank transmittance is larger than 12%. From our wafer data, it has been seen that the common process window from High T mask is 40nm bigger than that from the 6% attnPSM mask. In the elongated bar structure with smaller aspect ratio, 1.26, the 12% High T mask shows significantly less develop CD pull back in the major direction. Compared to the High T mask, the optimized new illumination condition for 6% attnPSM shows limited improvement in MEEF and the DoF through pitch. In addition, by using the High T mask blank, we have also investigated the SRAF printing, side lobe printing and the resist profile through cross sections, and no patterning risk has been found for manufacturing. As part of this work new 12% High T mask blank materials and processes were developed, and a brief overview of key mask technology development results have been shared. Overall, it is concluded that the High T mask, 12% transmission, provides the most robust and extendable lithographic solution for 10nm node and beyond.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.

Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.