Neuroprosthetic technology has made significant strides in restoring movement for paralyzed individuals by decoding motor cortex signals into commands for prosthetic limbs or exoskeletons. Although high-channel neural implants have enhanced prosthetic control and freedom of movement, the benefits of channel scaling are restricted by the absence of feedback and the steep learning curves required for users. To address this, sensory feedback from prosthetic sensors has been used to modulate the sensory cortex for more stable and accurate prosthetic control [1]. However, latency in data transmission, decoding, and feedback mapping hinders the system's effectiveness as a true closed-loop. To overcome these challenges, a disruptive approach has emerged that introduces rapid local feedback between the motor and sensory cortices [2]. Instead of relying on external sensor inputs, this method derives sensory feedback directly from motor signals and modulates stimulation in the sensory cortex, reducing latency and simplifying learning (Fig. 15.4.1 top). Animal studies using optogenetic feedback have shown faster motor target acquisition with this internal feedback [3]. While optogenetics cannot be easily adopted for humans, electrical stimulation is a viable alternative, though it presents challenges such as rejecting stimulation artifacts to avoid false modulation or positive feedback loops.

Large-scale neural interface ICs have tens of thousands of electrodes [1]–[3], enabling a wide range of applications including neural prostheses and therapeutic neuromodulation. However, the human brain contains 86 billion neurons and new frontiers in brain interfacing, such as understanding memory and cognition, will benefit from concurrent access to a million or more of implanted electrodes [4]. Modern microfabrication technologies, including silicon wafer thinning [1], allow for dense co-integration of electrodes and transistors on the same flexible substrate [1,4-6] and overcome the issue of the mega-scale electrode interconnect bottleneck [7]. The key remaining challenges are the low energy efficiency of neural ADCs and the high output data rate [4]. For example, one million inputs require 10nW/input ADC power - for a tissue-safe 10mW ADC total power budget [8], and a 200Gb/s wireless link - for 8b conversion at 25kHz [4]. However, the power dissipation of neural ADCs, either dedicated [9]–[12] or time-multiplexed [1-3,13], is over 50× higher, and implantable radios are at least 100× slower [14]–[15]. To address these challenges, neural spiking sparsity has been exploited in both off-line [16]–[17] and on-line [8], [18] methods of optimum electrode selection, but this leads to significant losses in recorded information [17] and requires $\text{near}-\cup \mathrm{W}/\text{inp}\lfloor\vert \mathrm{t}$ power due to static circuit biasing [8], [18], respectively.

Neural recording is fundamental to advancements in neuroscience and the development of brain-computer interfaces. Central to this process is the neural amplifier, a critical component that directly influences the quality and fidelity of neural signal acquisition. The amplifier's performance determines the noise level contaminating neural signals and ensures adequate amplification for accurate analog-to-digital conversion (ADC). However, conventional neural amplifiers face significant challenges. They typically require a constant biasing current, leading to inefficient power consumption, and are limited by a constrained gain-bandwidth product due to power budget restrictions. This paper addresses these challenges by delving into the essential requirements for neural amplifiers and discussing the limitations of traditional designs. We introduce a dynamic amplifier that not only surpasses the conventional gain-bandwidth trade-off but also effectively mitigates saturation issues caused by stimulation or motion artifacts. Furthermore, the proposed amplifier exhibits significantly lower thermal and 1/f noise compared to traditional static amplifiers. Our simulation results demonstrate that the proposed neural amplifier consumes less than 200nW of power, with a signal-to-noise-and-distortion ratio (SNDR) of 82.6dB at a 5kHz bandwidth. The amplifier also achieves an input-referred noise of 4.54 mu V-rms. Additionally, the noise-efficient factor is 1.1, highlighting the amplifier's noise performance and its suitability for high-fidelity neural signal acquisition.

The peripheral nervous system (PNS) facilitates communication between the brain and various organs. Advanced PNS neural interfaces can help in restoring motor functions for patients suffering from spinal cord injuries, amputations, and other conditions. The efficacy of these neural interfaces, and the precision of sensory activity decoding is heavily reliant on artificial intelligence techniques at the backend. Traditional machine learning techniques, such as feature-based classification, generally requires extensive feature engineering and domain expertise, and is often ineffective at handling very high-dimensional data. Additionally, convolutional neural networks (CNNs) tend to perform best when employing floating-point operations, which in-turn can be computationally intensive and less energy-efficient. Addressing these challenges, this paper presents a multiplierless spiking neural network (SNN) that utilizes fewer neurons to achieve higher accuracy. Leveraging the discrete firing characteristics of SNNs, we propose a hardware implementation model, trained on experimentally recorded action potentials from rat peripheral nerves. This demonstrates a significant improvement in Macro F1-score, reaching 0.89, over various CNNs while using 99.8% fewer parameters. It fully decodes three degrees of rat motion (dorsiflexion, plantarflexion, and pricking stimulation), showcasing the potential for efficient and accurate hardware integration. This work highlights a path towards the development of next-generation hardware-assisted neural interfaces.