Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary ‘all III–V’ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V DS |=0.5V. The p-type TFET (PTFET) has I ON =30µA/µm and I ON /I OFF =10 5 , whereas the n-type TFET (NTFET) has I ON =275µA/µm and I ON /I OFF =3×10 5 , respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V DD logic applications.

We present reliability analysis of the two most critical interfaces in III-V Heterojunction Tunnel FET (HTFET) design: (1) Tunnel Heterojunction is characterized in three-dimensional atomic scale resolution using Atom Probe Tomography. We explore the impact of tunnel junction abruptness and source dopant fluctuations on HTFET performance; (2) Extremely scaled Hi-K gate dielectric (sub-0.8 nm EOT: HfO2, HfO2-ZrO2 bilayer, and ZrO2)/ III-V channel interface is evaluated using Positive Bias Temperature Instability (PBTI) measurements. HfO2 based HTFET exhibits superior PBTI performance over ZrO2 based HTFET and shows lifetime improvement over III-V FinFET.

We demonstrate high frequency switching characteristics of TFETs based on the In0.9Ga0.1As/GaAs0.18Sb0.82 material system. These near broken-gap TFETs (NBTFETs) with 200nm channel length exhibit record drive current (I-ON) of 740 mu A/mu m, intrinsic RF transconductance (Gm) of 7000/jam, and a cut-off frequency (F-T) of 19GHz at V-DS=0.5V. Numerical simulations calibrated to the experimental data are used to provide insight into the impact of vertical architecture on switching performance of TFETs at scaled technology nodes.