For HfSiON/SiO2 n-type and p-type MOSFETs with a channel length L = 64 nm, the fast relaxation effect of oxide-trapped charges Q(ox) during interrupt for bias temperature instability (BTI) degradation measurement were investigated, and a model that compensated for this effect to predict lifetime t(L) was proposed. Experimental results show that the fast relaxation of Qox during threshold-voltage V-th measurement rapidly saturates within 1 s and is exponentially increasing for gate stress voltage V-g,V-str and exponentially decreasing for measurement duration t(m) but does not affect the BTI degradation mechanism. Using the V-g,V-str and t(m) dependence of Q(ox's) fast relaxation under BTI stress, t(L) prediction model was proposed to compensate the recovery effect by V-th measurement from BTI degradation measured in slow measurement (SM) condition with t(m) > 1 mu s. The proposed model increases the precision of the estimate of t(L) by considering the recovery effect of Qox even in SM. (C) 2020 The Japan Society of Applied Physics

A new circuit structure and control method for a high power interleaved dual-buck inverter are proposed. The proposed inverter consists of six switches, four diodes and two inductors, uses a dual-buck structure to eliminate zero-cross distortion, and operates in an interleaved mode to reduce the current stress of switch. To reduce the total harmonic distortion at low output power, the inverter is controlled using discontinuous-current-mode control combined with continuous-current-mode control. The experimental inverter had a power-conversion efficiency of 98.5% at output power = 1300 W and 98.3% at output power = 2 kW, when the inverter was operated at an input voltage of 400 VDC, output voltage of 220 VAC/60 Hz, and switching frequency of 20 kHz. The total harmonic distortion was < 0.66%, which demonstrates that the inverter is suitable for high-power dc-ac power conversion.

This paper evaluates how channel length L affects the drain avalanche hot carrier degradation (DAHC) degradation mechanism of HfSiON/SiO2 pMOSFETs that have strained Si/SiGe channel. DAHC degradation occurred as L was to reduced < 70 nm, and the amount of degradation increased as L decreased. In the early stage of stress, DAHC degradation increased positively due to generation of negative oxide charges -Q(ox), but gradually-generated interface states N-it neutralize -Q(ox), so a transition point occurs and eventually DAHC increases negatively after sufficient stress time t(s). The distribution of DAHC degradation was also analyzed after t(s) = 4000, 40000 s. The effects of additional generation of -Q(ox) and N-it on DAHC degradation contribute more near the drain edge than to the center region, and increase as L decreases. Therefore, further research on the DAHC degradation mechanism should be conducted to predict the reliability of HfSiON/SiO2 pMOSFETs with mechanical strain engineering. (C) 2020 The Japan Society of Applied Physics

In this work, a new active balancing circuit is proposed. This circuit consists of a cell-access network and an energy-transfer network. The cell-access network requires 2n + 6 switches, where n is the number of cells, and creates an energy-transfer path between unbalanced cells and the energy-transfer network. The energy-transfer network has double energy carriers and simultaneously implements cell-to-pack and pack-to-cell balancing operations without overlapping. As a result, a high power rate and fast balancing operation can be achieved by using two energy carriers in a single balancing circuit. The prototype of a proposed balancing circuit was built for six cells and then tested under various conditions; all cells in the state of charge (SOC) region of 70% to 80% were equalized after 93 min, and one charging/discharging period in the SOC region of 10% to 90% was increased by 8.58% compared to the non-balancing operation. These results show that the proposed circuit is a good way to balance charges among batteries in a battery pack.

The effect of HfSiON thickness on electron trap distributions under positive bias temperature instability (PBTI) was investigated in HfSiON/SiO2 nMOSFET. Trap distributions of HfSiON/SiO2 nMOSFET were observed by charging and discharging electrons at pre-existing or newly-generated traps. Experimental results show that the peak values of electron trap density shifted to deeper electron trap energy level (Et) with increasing stress field Estr and stress time ts. Compared to the Thick HfSiON device, the Thin HfSiON device had lower trap density and slower Et-shift; as a result, the Thin HfSiON device had lower threshold voltage-shift ∆Vth and larger power-law time exponent n of PBTI than the Thick HfSiON device. Low ∆Vth is beneficial for lifetime of HfSiON/SiO2 nMOSFET but large n is not, so the effect of HfSiON thickness on distribution of electron trap must be quantified to enable optimization of HfSiON thickness to yield reliable HfSiON/SiO2 nMOSFETs.

This paper describes a boost half-bridge DC-DC converter for photovoltaic system that reduces the input voltage and current ripples by using a 1:1 transformer and an auxiliary capacitor. The 1:1 transformer replaces the boost inductor in a previous boost half-bridge converter. The auxiliary capacitor is connected serially to the secondary coil of the 1:1 transformer, and resonates with the leakage inductance of the 1:1 transformer. The input voltage and current ripples are reduced by setting the switching frequency equal to the resonance frequency between the auxiliary capacitor and the leakage inductance, and by coupling the resonance current to the primary coil of the 1:1 transformer. The proposed converter had input voltage ripple less than 0.2 V-p.p, input current ripple less than 0.81 A(p.p), 5, and power-conversion efficiency higher than 94.5% when the converter was operated at input voltage of 30-50 V, output voltage of 400 V, output power of 30-300 W, and switching frequency of 46 kHz. These experimental results show that the proposed converter is well suited for photovoltaic micro-inverter applications that require a small input capacitor, low input voltage, high input current, high output voltage, and high power-conversion efficiency.

This paper proposes a bidirectional dc–dc converter for residential micro-grid applications. The proposed converter can operate over an input voltage range that overlaps the output voltage range. This converter uses two snubber capacitors to reduce the switch turn-off losses, a dc-blocking capacitor to reduce the input/output filter size, and a 1:1 transformer to reduce core loss. The windings of the transformer are connected in parallel and in reverse-coupled configuration to suppress magnetic flux swing in the core. Zero-voltage turn-on of the switch is achieved by operating the converter in discontinuous conduction mode. The experimental converter was designed to operate at a switching frequency of 40–210 kHz, an input voltage of 48 V, an output voltage of 36–60 V, and an output power of 50–500 W. The power conversion efficiency for boost conversion to 60 V was ≥98.3% in the entire power range. The efficiency for buck conversion to 36 V was ≥98.4% in the entire power range. The output voltage ripple at full load was <3.59 Vp.p for boost conversion (60 V) and 1.35 Vp.p for buck conversion (36 V) with the reduced input/output filter. The experimental results indicate that the proposed converter is well-suited to smart-grid energy storage systems that require high efficiency, small size, and overlapping input and output voltage ranges.

This paper presents an investigation of the effect of oxide-trapped charge on the anomalous drain avalanche hot carrier degradation of SiO2 dielectric nMOSFET. In contrast to the conventional degradation behavior, saturation threshold voltage degradation Delta V-th,V-sat sar decreased during the first 2000 s of stress, then increased because the polarity of the charge, which is trapped 60 nm away from the drain, changed from positive to negative over time. During the first 2000 s, the holes generated by impact ionization were transported to similar to 60 nm away from the drain by the lateral field, and were trapped there. Thereafter, the vertical oxide field varied with the change in the energy band diagram and this caused an increase in electron trapping over time. Then interface traps and electron trapping became dominant after 2000 s. To accurately predict the anomalous degradation, a model is proposed that includes an oxide-trapped charge, in addition to the interface traps that is considered in the conventional models.

This paper proposes a grid-connected single-stage micro-inverter with low cost, small size, and high efficiency to drive a 320 W class photovoltaic panel. This micro-inverter has a new and advanced topology that consists of an interleaved boost converter, a full-bridge converter, and a voltage doubler. Variable switching frequency and advanced burst control schemes were devised and implemented. A 320 W prototype micro-inverter was very compact and slim with 60-mm width, 310-mm length, and 30-mm height. In evaluations, the proposed micro-inverter achieved CEC weighted efficiency of 95.55%, MPPT efficiency >95% over the entire load range, and THD 2.65% at the rated power. The proposed micro-inverter is well suited for photovoltaic micro-inverter applications that require low cost, small size, high efficiency, and low noise.

This paper proposes a method to reduce turn-on and turn-off switching losses of a direct-current-direct-current (DC-DC) buck converter. A passive snubber circuit, which includes one inductor, one resistor, two diodes and three capacitors, was used to increase the power conversion efficiency. The maximum efficiency of the proposed converter for an output power of 120 W was measured as 96.33%, which is 0.62 ~1.46% higher than the conventional buck converter and other buck converters with the passive snubber circuits. The proposed snubber circuit operates stably under sudden changes in the load.

A wireless battery charging circuit is proposed, along with a new load estimation method. The proposed estimation method can predict the load resistance, mutual inductance, output voltage, and output current without any wireless communication between the transmitter and receiver sides. Unlike other estimation methods that sense the high-frequency AC voltage and current of the transmitter coil, the proposed method only requires the DC output value of the peak current detection circuit at the transmitter coil. The proposed wireless power transfer (WPT) circuit uses the estimated parameters, and accurately controls the output current and voltage by adjusting the switching phase difference of the transmitter side. The WPT prototype circuit using a new load estimation method was tested under various coil alignment and load conditions. Finally, the circuit was operated in a constant current and constant voltage modes to charge a 48-V battery pack. These results show that the proposed WPT circuit that uses the new load estimation method is well suited for charging a battery pack.

This paper investigates how interfacial layer (IL) thickness of HfSiON/SiO2 nMOSFETs affects their responses to positive bias temperature instability. Experimental results show that stress-induced traps and secondary-hole trapping were generated more in a thicker IL nMOS than in a thinner IL nMOS. From these results, the thicker IL nMOS had larger threshold voltage-shift AVd, and lower time exponent n than the thinner IL nMOS at the same oxide field E. At high E, the thicker IL nMOS had shorter lifetime (t(L)) due to larger Delta V-th than the thinner IL nMOS. At low E-ox, related to operating voltage, the thicker IL nMOS had longer tL due to lower n than the thinner IL nMOS. Thus, thickening the IL is applicable to increase t(L) of HfSiON/SiO2 nMOSFET.

This paper quantifies how mechanical stress induced by the hybrid shallow trench isolation affects negative bias temperature instability (NBTI) degradation of p-type channel MOSFETs (pMOSFETs) that have a strained Si/SiGe channel. As the channel length L decreased, the NBTI degradation decreased and electrical characteristics degraded. Experimental results indicate that tensile stress σt applied to the channel region decreased the energy band-gap by increasing the intrinsic carrier concentration. NBTI degradation was not affected by application of an oxide electric field to compensate for the charge that is induced differently in the Si channel during strong inversion. The distribution of the shift ΔVth of threshold voltage before and after NBTI stress in the channel region was also examined. As L decreased, the decrease of ΔVth was greater in the gate edge region than in the center region. These results show that the observed L-dependence of NBTI degradation characteristics were caused by σt in the channel region, and affected the gate edge region dominantly. Therefore, to achieve reliable high-k pMOSFETs with the strained Si/SiGe channel as L is scaled down, methods should be developed to control mechanical stress in the gate edge region.

A modularized design of an active charge equalizer and a charge equalization algorithm for a Li-ion battery pack are proposed in this paper. The equalizer consists of one module-balancing circuit and $M$ cell-balancing circuits, where $M$ is the number of modules in the battery pack. Each balancing circuit uses an inductor that is placed in a bridge of four bidirectional switches and works as an energy carrier, and uses a cell/module access network that enables energy transfer from one cell/module to another cell or module. The charge equalization between modules can be performed simultaneously with that between cells, so the proposed circuit can significantly reduce the time required to equalize the charges of all cells in the battery pack. The proposed circuit was tested under various charging/discharging conditions for a battery pack composed of four serially connected modules, with four serially connected cells per module. Experimental results show that the proposed circuit and algorithm comprise a good solution to balance a Li-ion battery pack.

This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that accurate extraction of the time exponent n of the power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage V-th. These obstructing effects were eliminated using Delta V(th)s obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n approximate to 1/4, an activation energy E-alpha = 0.04 eV for the fast recoverable degradation, and E-alpha = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed.

This paper proposes a circuit structure of bidirectional dc-dc converter. This structure uses two switches, two capacitors, a 1: 1 transformer, and a control circuit for pulse-frequency modulation. The windings of the transformer are connected in a series-aiding configuration to reduce current ripples and to increase power conversion efficiency eta(epsilon). The capacitors and the leakage inductance of the transformer provide soft-switching conditions. When the proposed converter was designed to operate at a switching frequency of 110-240 kHz, input/output voltages of 100-400 V, and output power P-o of 30-300 W, eta(epsilon) was >= 97% for P-o >= 90W and 93.5% at P-o = 30 W. Experimental results show that the proposed converter is suitable for use in photovoltaic power conversion systems and energy storage systems.

This paper presents a method to measure the threshold voltage degradation ΔVth along the channel direction due to electrical stress in MOSFETs. This method uses ΔVths measured after electrical stress at different drain bias Vds, and calculated the depletion length Ldep into the channel for each condition under which ΔVth is measured. By substituting ΔVth and Ldep into the proposed equation, the amount of degradation generated in each region of the MOSFET channel can be calculated. The ΔVth profiles of OFF-state stress and negative bias temperature instability in pMOSFET and hot carrier injection in nMOSFET were extracted using the proposed method. The degradation profiles correspond well with each stress characteristic.

A quasi-resonant passive snubber for the conventional dc-dc step-down converter is proposed. The snubber uses six passive components to achieve a zero-current turn-ON and zero-voltage turn-OFF of the switch, and to suppress the reverse recovery current of diode. At input voltage of 200 V, output voltage of 100 V, output power of 300 W, and switching frequency of 190 kHz, the snubber increased the power conversion efficiency eta(e) by 2.8% and stabilized the temperature of MOSFET switch at similar to 68 degrees C. The snubber worked well for both MOSFET and insulated gate bipolar transistor (IGBT) switches without increasing the voltage stress. These experimental results show that the proposed snubber is very helpful for improving eta(e) of a dc-dc step-down converter that operates at a high frequency.

This paper proposes a fast and accurate method to measure the constants a and n of the power law ∆Vth=atn for HfSiON/SiO2 dielectric nMOSFETs under positive bias temperature instability (PBTI), where ∆Vth is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS), measures ∆Vth vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage Vg,str, then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. Vg,str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime tL at an operating voltage Vop was estimated using the power law. The estimated tL=1.67×108s was quite close to tL=1.74×108s estimated using CVS, and to tL=1.72×108s estimated by extrapolating the ΔVth vs. t curve measured at Vg,str=Vop=1.2V to ΔVth=200mV. The time required for measurement was 900s, compared to 30,000s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI.