Microgrids comprising grid-following (GFL) inverters and Andronov-Hopf oscillator (AHO)-based grid-forming (GFM) inverters have emerged as a promising architecture. However, grid voltage sags may drive the system into synchronization instability. To address this challenge, a dynamic power-angle model of such a microgrid is established, and the effects of AHO inverter power setpoints and GFL inverter current references on synchronization stability are analyzed. Then, a synchronization stability constrained power command optimization method is proposed to reconstruct the stable equilibrium point of the system during faults while minimizing command changes, transient voltage and frequency excursions, and deviations from grid-code requirements. Sectional energy functions are also constructed to quantitatively evaluate the stability margin. Hardware-in-the-loop tests validate the proposed analysis and control method. In addition, the proposed control method is extended to a droop-GFL microgrid, and the corresponding results are compared with those of the AHO-GFL system.
This work presents a digital fully integrated voltage regulator (DFIVR) with four-ring process, voltage, and temperature (PVT) compensation and ESR-free operation. 3D-integrated DrMOS stages, coordinated by a centralized digital pulse width modulator (DPWM) controller for per-phase drive, are designed to support a total current of 80 A and are experimentally validated from 20–80 A. A slope-tracking DPWM with synchronized delay calibration ensures fine on-time control. Measurements show <5 mV ripple and 150 ps on-time resolution, achieving an analog-to-digital converter (ADC) integral nonlinearity (INL) of ±0.4 least significant bit (LSB), and a DPWM differential nonlinearity (DNL) of ±0.25 LSB under PVT variations. A 22×22×3.5 mm³ module, including four 600 nH inductors, eight DrMOS power stages, a DPWM controller, and a 10 mF MLCC (including a 4.7-mF output reservoir), achieves 88.6 W/cm³, enabling scalable 3D chiplet regulation.
High-frequency injection (HFI) based sensorless method has been widely implemented digitally. However, the discretization of HF signals brings significant challenges to enhancing the observation performance. Besides, excessive HF excitation current is typically considered to be inevitable for sufficient signal-to-noise ratio (SNR). To realize the HF excitation current reduction without digital SNR degradation, this paper applies discrete-domain frequency analysis to HFI, where the aliasing induced superposition gain is revealed and actively exploited for the first time. The superposition gain in digital HF signals beyond the original analog signals can be actively induced by the aliasing effects. Moreover, the speed-dependent optimal injection frequency is demonstrated, which exhibits the highest digital HF current superposition gain. Based on these findings, the SNR maintained variable frequency injection based sensorless method is proposed, which achieves HF excitation current reduction without SNR degradation. The convergence of the proposed method containing supra-Nyquist signals is also proved. Finally, the experiments validate the proposed excitation reduced sensorless method.
The active neutral-point-clamped (ANPC) three-phase dual active bridge topology allows existing 650-V GaN devices to be used in high-voltage dc-dc applications, enabling high efficiency and power density. However, device non-idealities cause midpoint voltage ($V_{\text{mid}}$) imbalances. A reversal of the control-to-$V_{\text{mid}}$ gain polarity destabilizes midpoint regulation under conventional proportional-integral (PI) control. In this paper, a model-free extremum-seeking (ES) controller is proposed that dynamically tracks the plant gradient to adaptively toggle loop polarity. Compared to threshold-based polarity-inversion (TPI) controllers, which suffer from voltage drift, the ES approach maintains robust $V_{\text{mid}}$ regulation during rapid load transients. The controller is validated on an 8-kW, 300-kHz, liquid-cooled GaN-based prototype, achieving 96% peak efficiency at 7.5kW and stable $V_{\text{mid}}$ balance across a wide load range.
The increasing penetration of inverter-based renewable energy systems requires grid-forming (GFM) inverters to maintain stable operation under fault conditions. However, their transient stability is significantly challenged when current-limiting mechanisms are activated, particularly when the power angle exceeds the unstable equilibrium point (UEP). To address this issue, an adaptive power-angle resetting (APAR) strategy is proposed to enhance post-fault recovery performance without relying on grid impedance information. The proposed method decouples the power-angle dynamics from the conventional power synchronous loop(PSL), enabling direct regulation of the power angle through an integrator resetting mechanism. Furthermore, the operating region is partitioned according to system states, and an adaptive adjustment scheme is developed to regulate the power angle under different fault conditions. And the Lyapunov energy-based stability analysis demonstrated that this proposed method can drive the system state to converge to stable operation point. Compared with existing approaches, the proposed strategy effectively suppresses post-fault oscillations, accelerates transient recovery, and maintains robustness under grid phase jumps. The effectiveness of the proposed method is validated through both simulation and experimental results.
The growth of electric vehicles (EVs) is driving new technological shifts, incorporating advanced control solutions in fast charging stations (FCSs) that expand their functionalities and provide greater operational flexibility. Specifically, these stations can operate as an uninterruptible power supply (UPS) to sustain critical local loads during grid contingencies. This paper implements a hybrid grid-forming (GFM) control approach for multifunctional FCSs capable of operating in both grid-connected and islanded conditions. Under this architecture, the system specifically addresses critical DC bus voltage overshoots resulting from reduced control bandwidth and sudden DC load variations. To mitigate these limitations, a DC-link direct compensation strategy is proposed. This parallel loop introduces a fast-acting current-injection mechanism that bypasses the slow inertia of the traditional droop branch, rapidly modifying the AC current reference to stabilize the DC bus. A comprehensive bottom-up modeling approach is detailed to support the control design. Experimental results for a 10 kW prototype validate the proposed method, demonstrating a significant 32.4 % reduction in DC voltage overshoot during load disconnection while ensuring stable, continuous operation across different grid scenarios.
Constant current (CC) DC power distribution is widely used in seafloor applications owing to its fault tolerance and high robustness. These systems are configured as daisy-chain networks, with discrete nodes drawing power in series. As the number of power nodes increases, particularly with the introduction of switching constant current to constant voltage (CC/CV) converters, system oscillation issues become increasingly prominent, and research in this system remains almost entirely unexplored. This paper establishes the impedance model for constant-current DC systems for the first time, which also incorporates the parasitic parameters of seafloor cables, providing a modeling basis for subsequent research. The impedance characteristics of each component are analyzed and summarized to support system stability analysis, rapid assessment, and oscillation suppression. In particular, the impedance features of shore-based DC current source assist in identifying the phase crossover frequency that trigger system oscillations. Also, a specific-band reduced-order compensated virtual impedance control method is proposed to suppress oscillations. The power-decoupled reduced-order compensation function eliminates the adverse effects of attached control loops and reduces the computational burden. Meanwhile, specific-band phase regulation is adopted to effectively enhance the compensation performance of virtual impedance. Finally, a 1 A multi-node constant-current DC experimental system is established, which verifies the accuracy of the model, the correctness of the stability analysis, as well as the effectiveness and scalability of the proposed control method.
This paper presents a model-driven electro-thermal design methodology for optimizing hybrid Totem-Pole Bridgeless power factor correction (PFC) converters employing both high-frequency SiC-MOSFETs and line-frequency silicon-controlled rectifiers (SCRs). The co-location of these dissimilar semiconductors on a shared thermal system induces complex electro-thermal interactions that conventional decoupled analysis fails to capture, thus hindering performance optimization. To address this, the proposed methodology utilizes a comprehensive, coupled electro-thermal model as an active design driver rather than a post-design verification tool. This approach enables a systematic, multi-objective optimization of component-level losses and the proactive management of thermal crosstalk between the SiC and SCR devices. Experimental results from a 3.3 kW hardware prototype confirm the methodology, achieving a competitive peak efficiency of 98.05%. Thermal measurements provide direct empirical evidence of the dominant thermal crosstalk from the heat-generating SiC-MOSFETs to the adjacent SCRs. Furthermore, the results reveal that significant temperature imbalances are governed by the physical component layout rather than by electrical symmetry. The primary contribution is a validated, system-level design principle: in a thermally-coupled hybrid converter, the junction temperature of a low-loss secondary device (the SCR) is governed predominantly by the efficiency of the adjacent dominant heat source (the SiC-MOSFET) rather than by its own dissipation. This shared-heatsink coupling is quantified with a closed-form coefficient, and the predicted temperatures are verified to within 8% of thermographic measurements.
As critical components in electromagnetic compatibility (EMC) filters, X2 film capacitors play an essential role in ensuring EMC compliance in power electronics. However, existing aging approaches are generally limited by selected-frequency measurements or incomplete aging-dependent parameter coverage, restricting wideband performance assessment. This paper proposes a wideband impedance degradation model for X2 film capacitors under AC electro-thermal-humidity stress, covering 20 Hz–110 MHz. Accelerated aging tests are conducted to characterize the impedance evolution and underlying degradation mechanisms. A lumped-parameter model is established by incorporating capacitance, equivalent series resistance, equivalent series inductance, and aging-dependent parallel insulation resistance, which is often neglected or treated as constant in existing aging models. The inter-sample degradation variability is statistically characterized using Weibull distributions and propagated through the impedance model via Monte Carlo simulation, generating percentile-based uncertainty bands. The model is applied to a CLC EMC filter, and the predicted differential-mode attenuation degradation is experimentally verified. Thermal analysis further shows that single-frequency characterization can substantially underestimate capacitor losses and thermal risk under wideband harmonic excitation. The proposed model supports aging-aware performance prediction and reliability-oriented design for EMI and EMC applications.
Current imbalance among parallel-connected power devices can lead to increased switching losses, aggravated thermal stress, and reduced reliability in high-power converters. This paper proposes a passive compensation circuit to mitigate transient current imbalance among parallel-connected power devices. The proposed circuit employs Rogowski coils to sense device current variations and modulate the gate currents during switching transients, thereby driving the device currents toward a closer match. The operating principle of the compensation circuit is analyzed using equivalent circuit models for both two-device and multi-device configurations. The analysis reveals that the induced electromotive forces generate gate extraction currents, forming a proportional-like feedback mechanism that acts on the device currents. Experimental validation is conducted using buck converter prototypes with two and four parallel-connected devices. Controlled current imbalance is introduced through threshold voltage mismatch and source parasitic parameter mismatch. Experimental results demonstrate that the proposed compensation circuit consistently reduces switching energy imbalance among parallel-connected devices. The proposed solution offers a fully passive approach for mitigating transient current imbalance, contributing to improved reliability in parallel device applications.
Due to the demand of simultaneously handling multiple objectives including current tracking, neutral point (NP) balancing and flying capacitor (FC) voltage balancing, the control of hybrid seven-level converter cascaded by three-level T-type converter and H-bridge (T2C-HB) is formulated as a multi-objective optimization problem (MOOP). Conventionally, model predictive control (MPC) applies weighting factors (WFs) to reformulate MOOP as a single-objective optimization problem. However, due to differences in the physical units of the objectives, WF selection typically relies on empirical trial-and-error. In addition, under varying operating conditions, constant WFs fail to adequately coordinate all control objectives, limiting the adaptability and system performance. To overcome this limitation, a reinforcement learning (RL)-based hierarchical MPC approach is proposed, replacing WFs with explicit admissible thresholds. Control objectives are hierarchically structured, and RL agent dynamically adjusts thresholds based on real-time deviations, achieving a trade-off in different control objectives. Both simulation and experimental results validate the effectiveness of the proposed approach.
Wide-bandgap devices impose severe constraints on gate driver isolation, adding extremely fast voltage transients to already stringent electrical requirements. This work introduces a bidirectional isolated communication strategy based on a single planar transformer. The approach relies on a simple push-pull circuit to generate customizable pulses. The associated protocol exploits pulse length and polarity to transmit control and fault signals, as well as additional feedback data such as module temperature. Bidirectional communication over a single channel inherently leads to message collisions, which are analyzed through simulation and mitigated by combining polarity alternation with an appropriate choice of pulse duration. Voltage transients impact is characterized and integrated into the decoding method. Reliable operation was demonstrated up to 300kV/μs without any failure. Partial discharge tests certify reinforced insulation up to 2.157kV, with creepage and clearance distances of 19mm. The system achieves a data rate of 350kB/s, a propagation delay of 470ns, and a jitter of 45ns. Compared with conventional solutions, the proposed approach uniquely combines a bidirectional protocol with planar transformer technology, allowing the design of a transformer with insulation thickness, creepage, and clearance adapted to specific application requirements.
In high-power converters, series-connected IGBTs exhibit dynamic voltage imbalance during turn-off, especially in the tail stage, leading to uneven voltage stress and energy dissipation. Although conventional RC snubber circuits are commonly used to suppress overvoltage during the tail stage, they introduce additional power dissipation and add design complexity. This article reveals that the tail-stage voltage deviation ΔVtail is fundamentally linked to the mismatch in residual tail charge Qtail and can be interpreted as an external manifestation of internal charge imbalance. Based on this insight, a stored-charge-regulated gate-delay control strategy is proposed, in which ΔVtail is used as the feedback signal for closed-loop delay adjustment. The proposed method indirectly regulates Qtail, improves stored-charge distribution, and enhances voltage sharing over the turn-off transient without using RC snubbers. Experimental results confirm that the proposed strategy maintains high effectiveness and adaptability across diverse operating conditions, even in the absence of RC snubber circuits. It effectively constrains the maximum ΔVtail to approximately 5%, thereby enhancing energy efficiency and system reliability, while enabling active voltage and energy balancing during the tail stage.
The thermal management of high-frequency magnetic components is an important design challenge in modern power electronics due to the drive toward higher power density. Traditional temperature monitoring methods, including invasive sensors and indirect thermal models, can be affected by electromagnetic interference or limited transfer across physical configurations. This work formulates steady-state ferrite-core temperature estimation as an inverse thermomagnetic sensing problem using a physics-aware vision transformer (PA-ViT). The synchronized open-circuit sensing-winding voltage and primary excitation current are reconstructed into dynamic $B$–$H$ responses and encoded as time-density hysteresis images (TDHIs). The Trajectory-Guided Attention Mask (TGAM) uses a deterministic trajectory-density mask derived from the TDHI to modulate the extracted visual features before tokenization, while cycle energy and excitation frequency are encoded into a separately formed physical token before fusion with the visual tokens. Under the controlled open-circuit magnetic-characterization condition, material-specific results are reported for TDK N87 and Ferroxcube 3C90, together with within-material evaluation on the corresponding Princeton MagNet subsets. On the self-built N87 test subset, PA-ViT yields a mean absolute error (MAE) of $1.22^\circ \text{C}$. Additional tests consider non-sinusoidal waveforms and additive white Gaussian noise (AWGN) synthetically applied to the measured signals, providing further evidence under the evaluated conditions.
This paper proposes a hybrid LC resonant circuit solution based on the active impedance module. Compared to passive resonant circuits with fixed resonant frequencies, which are prone to component parameter shift, the proposed hybrid LC resonant circuit can adjust the resonant frequency. It also maintains frequency stability under component parameter shift and different operating conditions. The paper further presents a control method for the resonant frequency and analyzes its impedance characteristics. Based on the proposed circuit solution and design process, a light-weight hybrid LC resonant circuit prototype is developed. To verify the hybrid LC resonant circuit, a 4000-W single-phase AC-DC converter test platform is constructed. Then, the feasibility of the proposed solution is verified in both steady-state and dynamic experiments.
Series partial power converters (S-PPCs) exhibit high efficiency in battery energy storage systems. Nevertheless, conventional topologies employing a fixed interconnection structure and unipolar switches are generally restricted to either step-up or step-down operation. Moreover, in the proximity of the unity-gain region, the duty cycle or phase-shift angle tends to approach its extreme boundaries, thereby aggravating the design challenges and substantially limiting the converter's voltage adjustment capability. To address these issues, a triple-active-bridge (TAB) based S-PPC featuring a differential series compensation architecture is proposed in this letter. By decoupling the voltage compensation requirement into two independent port voltages, the proposed strategy maintains the control variables away from zero, inherently bypassing the constraints of duty cycle or phase-shift angle. Consequently, the proposed topology achieves both the precise wide-range step-up/down regulation and the smooth mode transition. Experimental results from a 200-W prototype validate the proposed architecture, demonstrating excellent steady-state performance and an ultrahigh peak system efficiency of 99.4%.
A high-frequency common-mode (CM) resonance peak appears in the MHz range of the noise spectrum due to the impedance interaction between parasitic capacitances and inductances in power converters. Conventional suppression methods, such as increasing the filter inductance or adding a parallel RL damping branch, inevitably increase inductance and size, thereby increasing the suppression cost and reducing the power density of converters. The imaginary part of the magnetic core's complex permeability results in an equivalent resistance. This resistance exhibits a frequency-dependent characteristic, being relatively high at high frequencies while remaining low at low frequencies. Based on this characteristic, this letter proposes a simple and compact CM resonance damping method. First, the damping mechanism of the proposed method is analyzed. Then, the negative impact of the core's equivalent inductance on resonance suppression is evaluated, and the corresponding design method is further developed. Experiments on a 40-kW dc-dc converter verify the effectiveness of the proposed method and its advantages in reducing volume and weight.
