With the continuous scaling-down of integrated circuit feature sizes, inverse lithography technology (ILT), as the most groundbreaking resolution enhancement technique (RET), has become crucial in advanced semiconductor manufacturing. By directly optimizing mask patterns through inverse computation rather than rule-based local corrections, ILT can more accurately approximate target design patterns while extending the process window. However, current mainstream ILT approaches—whether machine learning-based or gradient descent-based—all face the challenge of balancing mask optimization quality and computational time. Moreover, ILT often faces a trade-off between imaging fidelity and manufacturability; fidelity-prioritized optimization leads to explosive growth in mask complexity, whereas manufacturability constraints require compromising fidelity. To address these challenges, we propose an iterative deep learning-based ILT framework incorporating a lightweight model, ghost and adaptive attention U-net (EAAUnet) to accelerate runtime and reduce computational overhead while progressively improving mask quality through multiple iterations based on the pre-trained network model. Compared to recent state-of-the-art (SOTA) ILT solutions, our approach achieves up to a 39% improvement in mask quality metrics. Additionally, we introduce a mask constraint scheme to regulate complex SRAF (sub-resolution assist feature) patterns on the mask, effectively reducing manufacturing complexity.

Logic locking is an efficient defense against attacks to the intellectual property of integrated circuits. However, in recent years, boolean satisfaction based attack (SAT attack) and a structural based attack named Valkyrie were proposed. As far as we know, most of the locking methods failed to achieve security for both of them and keep an acceptable overhead. In this paper, we present a self-adaptive str iped-function logic locking method named SFLL-AD, based on repeatedly modifying the structure of the encryption block to a form that: (1) permits splitting and dispersing the encryption block across the netlist to have resilience to Valkryie (2) and guarantees not losing SAT resilience. Experimental results of our mehtod confirm the security to both attacks and show a small overhead (about 10% on average).

In large-scale natural gas liquefaction, minimizing specific energy consumption has consistently been a primary objective. This study aims to develop a large-scale natural gas liquefaction process that balances energy efficiency and cost-effectiveness, presenting a viable option for industrial production. By employing a refrigerant strategy of "propane + mixed refrigerant + mixed refrigerant", a novel large-scale natural gas liquefaction process based on triple refrigeration cycles (TRC) is proposed. To address the challenge of boil-off gas (BOG) reliquefaction, the TRC process is further refined to integrate BOG re-liquefaction (TRC-BR). Thermodynamic models are built for the proposed TRC and TRC-BR processes, as well as the propane pre-cooled mixed refrigerant (C3MR) and AP-X processes as baseline cases. Global optimization is conducted using the Particle Swarm Optimization (PSO) algorithm, with the specific power consumption (SPC) serves as the objective function. The results reveal that the SPC of the TRC and TRC-BR processes are 0.2726 and 0.2704 kWh/kg-LNG respectively. Compared with the C3MR and AP-X processes, the SPC of the TRC decrease by 1.54% and 4.84%, respectively. The total investments for the TRC and TRC-BR processes are estimated at a similar level compared to the baseline cases, demonstrating their significant potential for industrial application.

Logic locking is an integrated circuits (ICs) protection technique that thwarts reverse engineering, IC overproduction, and IP piracy caused by untrusted foundry and end-users. After Boolean Satisfiability (SAT) solver was applied to crack the keys, researchers proposed various defenses against SAT, approximate, and removal attacks. The Valkyrie attack based on structural analysis has been recently presented that breaks all the existing combinational logic locking techniques. In this letter, we present Structural Interference Logic Locking (SILL) technique. SILL adds interference logic combined with traditional cryptographic logic to drive the primary output, which enables defense against structural attacks by assigning keys to the cryptographic and interference logic according to rules. According to the experimental results, SILL is between (k-4)-secure and (k-2)-secure against SAT Attack while defending against Valkyrie attack.

In this letter, a structural analysis attack is explored as the first kind of attack to disclose the secret key of the circuit encrypted by the latest obfuscation technique JANUS-HD. By extracting the finite state machine (FSM) diagram from the circuit and converting structural traces into constraints, the secret key can be deduced by the CP-SAT solver within a few minutes or even seconds in most cases. Incorrect keys can be further pruned by sequential equivalence checking with several oracles in case more than one key is obtained. The entire attack procedure lasts no longer than a few hours even for an FSM with 4096 states.

Energy efficiency management and fault tolerance are two key issues that need to be handled wisely in heterogeneous multiprocessor real-time systems. The paper uses dynamic power management (DPM) and dynamic voltage frequency scaling (DVFS) techniques to manage energy efficiency, and standby-sparing technique is used to achieve fault tolerance. This paper proposes two task scheduling algorithms: max reliability standby-sparing (MRSS) and dynamic reallocation fault tolerant (DRFT). MRSS expresses the dependency between primary tasks and backup tasks by constructing new matrices, while ensuring that the priority of the main task is higher than that of the backup task. DRFT reallocates tasks when fault is detected to maintain the reliability of the system. Finally, simulation experiments show that the algorithm can save up to 53% of energy compared with the no-power management scheme.

With the development of industrial networks, the demands for strict timing requirements and high reliability in transmission become more essential, which promote the establishment of a Time-Sensitive Network (TSN). TSN is a set of standards with the intention of extending Ethernet for safety-critical and real-time applications. In general, frame replication is used to achieve fault-tolerance, while the increased load has a negative effect on the schedule synthesis phase. It is necessary to consider schedulability and reliability jointly. In this paper, a heuristic-based routing method is proposed to achieve fault tolerance by spatial redundancy for TSNs containing unreliable links. A cost function is presented to evaluate each routing set, and a heuristic algorithm is applied to find the solution with higher schedulability. Compared to the shortest path routing, our method can improve the reliability and the success rate of no-wait scheduling by 5–15% depending on the scale of topology.

作为智能电力系统建设的核心,电力相关芯片的快速普及使得芯片的能耗也成为了电力系统的能耗中不可忽视的一部分.针对电力终端多核芯片的能耗问题,首先基于原有的任务调度技术,提出了考虑任务运行时间概率分布(task execution time probability,TETP)的任务内调度方案;并利用混合整型线性规划(mixed integer linear program-ming,MILP)将该问题建模,以求用数学方法得到该调度方案能获得的最优解.最后,通过建立实验验证平台对此方法加以验证,结果显示文中提出的调度方案相比于传统调度方案平均减少的能耗在30％以上.

There is a great deal of interests in multivariate approaches which may offer a necessary, and often sufficient, data analysis technique in many fields such as analytical chemistry, biology and environmental chemistry. However, few of these multivariate approaches have paid attention to the nonnegativity constraint in the decomposition process. In this paper, a novel bound constrained optimization method was proposed for three-way chemical data analysis. In this method, nonnegative matrix factorization was introduced to replace the traditional trilinear decomposition to provide the constraints on the nonnegative boundary on excitation-emission matrix spectra data. And the least-squares problem was transformed into a bound constrained optimization problem which can be solved by projected gradient methods. The alternating least squares were applied during each optimization iteration to obtain the individual components. Analysis of simulated three-way arrays indicated that the proposed method has a better performance than parallel factor analysis and alternating trilinear decomposition methods in nonnegativity. Experiments of real excitation-emission matrix spectra data also show that the proposed method is robust with the background interferences in practical applications.

Assembly precision analysis is one of the fundamental technologies used for controlling the assembly quality of products. Existing assembly precision analysis methods focus on identifying the assembly deviation caused by manufacturing errors of parts. They place less emphasis on the influencing factors in the assembly process, which significantly affect the reliability of the analytical results. Additionally, the lack of assembly knowledge for part models leads to a low efficiency of the assembly simulation. To address these problems, this paper presents an assembly precision analysis method based on a general part digital twin model (PDTM). The proposed PDTM integrates multi-source heterogeneous geometric models and maps assembly information from assembly semantics to geometry elements, allowing automatic assembly positioning of parts and improving the efficiency of assembly simulation. In addition to the manufacturing errors, the assembly-positioning error and mating-surface deformation are considered to quantify the impact on the key characteristics of the assembled product. Based on the real mating status simulation for the mating surfaces, the uncertainty of assembly positioning in an actual assembly is simulated by combining the small displacement torsor (SDT) theory and the Monte Carlo method. Furthermore, the mating-surface deformation can be superposed to the result of the assembly-gap calculation, improving the reliability of the analytical results. Finally, a prototype system and a case study involving a load sensitive multi-way valve assembly process are introduced to demonstrate the applicability of the proposed method.

A linear and exponential (sqrt2 rule) combined curve fitting (CF) is proposed for low-energy shared cache partitioning. Considering cache's inherent characteristics between cache miss rate and its size, function with an exponent of (1-sqrt2) fits the region of non-linear high-utility cache size, while linear function fits both regions of linear high-utility and low-utility cache size. Using the fitted functions, we proposed a scheme with purely mathematical formulization of energy consumption, which helps fast and efficient shared cache partition. Experimental results show that CF based shared cache partitioning scheme achieves up to 34.5% energy savings compared with other traditional techniques. Moreover, our approach has a high prediction accuracy for the shared cache miss rate and the energy.

Cache partitioning is a successful technique for saving energy for a shared cache and all the existing studies focus on multi-program workloads running in multicore systems. In this paper, we are motivated by the fact that a multi-thread application generally executes faster than its single-thread counterpart and its cache accessing behavior is quite different. Based on this observation, we study applications running in multi-thread mode and classify data of the multi-thread applications into shared and private categories, which helps reduce the interferences among shared and private data and contributes to constructing a more efficient cache partitioning scheme. We also propose a hardware structure to support these operations. Then, an access adaptive and thread-aware cache partitioning (ATCP) scheme is proposed, which assigns separate cache portions to shared and private data to avoid the evictions caused by the conflicts from the data of different categories in the shared cache. The proposed ATCP achieves a lower energy consumption, meanwhile improving the performance of applications compared with the least recently used (LRU) managed, core-based evenly partitioning (EVEN) and utility-based cache partitioning (UCP) schemes. The experimental results show that ATCP can achieve 29.6% and 19.9% average energy savings compared with LRU and UCP schemes in a quad-core system. Moreover, the average speedup of multi-thread ATCP with respect to single-thread LRU is at 1.89.

Energy optimization plays an increasingly critical role in designing an embedded real-time multiprocessor System on Chip (MPSoC). Dynamic Voltage Frequency Scaling (DVFS) and Dynamic Power Management (DPM) are preferable techniques to optimize energy consumption. However, previous DVFS and DPM algorithms were mostly designed for inter-task scheduling, without sufficient exploration on intra-task scheduling for further energy reduction. This paper presents a new intra-task scheduling approach considering the probabilistic distribution of task execution time, and it optimizes the mathematical expectation of power consumption (expected power consumption) for periodic dependent tasks with uncertain execution time running on MPSoCs using DVFS and DPM. The energy-efficient scheduling problem can be formulated by means of mixed integer linear programming (MILP) with the proposed technique. Moreover, we also propose a technique to compress the exploration space by reorganizing the probabilistic profiling information of all tasks. Our experimental results on synthetic and realistic benchmarks show that the proposed approach achieves up to 30 percent energy savings compared with other existing methods.

Energy saving and system reliability are two crucial issues for designing modern multiprocessor systems. There has been reliability-aware power management with dynamic voltage-frequency scaling (DVFS) schemes in recent studies. However, they are limited to optimization under the impact of DVFS on energy and reliability and have not considered reducing the non-negligible leakage energy consumption. In this paper, we focus on co-management of system reliability and total energy for applications with precedence constrained tasks on heterogeneous multiprocessor real-time systems. We first investigate the impact of energy management techniques on both reliability and energy of the systems using task recovery for fault tolerance and then propose an Energy-efficient Fault-tolerant Scheduling (EFS) scheme integrated with power mode management, which can mitigate the negative impact of DVFS on system reliability. To obtain the optimal energy-efficient reliability-guaranteed scheduling for pre-mapped applications on systems considering various realistic issues, we build mixed integer linear programing formulations with the proposed EFS scheme. To address mapping and scheduling for energy-efficiency and fault-tolerance, we finally develop a framework implemented by a List-based Binary Particle Swarm Optimization algorithm. The extensive comparative evaluations for synthetic and realistic benchmarks show that our approaches outperform several related studies in terms of energy consumption and system reliability.

Energy optimization for periodic applications running on safety/time-critical time-triggered multiprocessor systems has been studied recently. An interesting feature of the applications on the systems is that some tasks are strictly periodic while others are non-strictly periodic, i.e., the start time interval between any two successive instances of the same task is not fixed as long as task deadlines can be met. Energy-efficient scheduling of such applications on the systems has, however, been rarely investigated. In this paper, we focus on the problem of static scheduling multiple periodic applications consisting of both strictly and non-strictly periodic tasks on safety/time-critical time-triggered multiprocessor systems for energy minimization. The challenge of the problem is that both strictly and non-strictly periodic tasks must be intelligently addressed in scheduling to optimize energy consumption. We introduce a new practical task model to characterize the unique feature of specific tasks, and formulate the energy-efficient scheduling problem based on the model. Then, an improved Mixed Integer Linear Programming (MILP) method is proposed to obtain the optimal scheduling solution by considering strict and non-strict periodicity of the specific tasks. To decrease the high complexity of MILP, we also develop a heuristic algorithm to efficiently find a high-quality solution in reasonable time. Extensive evaluation results demonstrate the proposed MILP and heuristic methods can on average achieve about 14.21% and 13.76% energy-savings respectively compared with existing work.