High density microprocessor packages are being deployed to achieve system performance improvements. However, the non-uniform heat dissipation characteristics of such packages has led to renewed interest in vapor chambers and heat pipes for heat spreading and transport. In this paper an approach to model the thermo-hydrodynamic performance of vapor chambers for cooling of microprocessor packages is presented. Model validation against data available in literature showed a very good agreement. The validated model was then used to study the performance sensitivity to vapor chamber design and operational parameters such as wick thickness, wick type, evaporator side heat input and condenser side heat extraction.

Manifold microchannel heat sinks can dissipate high heat fluxes at moderate pressure drops, especially during two-phase operation. High-aspect-ratio microchannels afford a large enhancement in heat transfer area; however, the flow morphology in manifold microchannels during two-phase operation, as well as the resulting thermal performance, are not well understood. In this work, a single manifold microchannel representing a repeating unit in a heat sink is fabricated in silicon with a bonded glass viewing window. Samples of different channel lengths (750 mu m and 1500 mu m) and depths (125 mu m, 250 mu m, and 1000 mu m) are considered; channel and fin widths are both maintained at 60 Am. Subcooled fluid (HFE-7100) is delivered to the channel at a constant flow rate such that the fluid velocity at the inlet is similar to 1.05 m/s in all cases. A high-speed camera is used to visualize the two-phase flow in the channel through the glass sidewall; an infrared camera measures the temperature distribution on the opposite channel sidewall. The flow visualizations reveal that vapor nucleation occurs at stagnation regions below the manifold near the inlet plenum and at both corners adjacent to the channel base. For deep channels (1000 mu m), at sufficiently high heat fluxes, vapor completely covers the base of the channels and liquid does not re-wet the surface in this region. This newly identified vapor blanketing phenomenon causes a significant decrease in performance and an increase in the measured channel wall temperatures. This study reveals the critical role of the two-phase flow morphology in manifold microchannel heat sink design. (C) 2020 Elsevier Ltd. All rights reserved.

High-heat-flux removal is critical for the next-generation electronic devices to reliably operate within their temperature limits. A large portion of the thermal resistance in a traditional chip package is caused by thermal resistances at interfaces between the device, heat spreaders, and the heat sink; embedding the heat sink directly into the heat-generating device can eliminate these interface resistances and drastically reduce the overall thermal resistance. Microfluidic cooling within the embedded heat sink improves the heat dissipation, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures. To enable multichip stacking and other heterogeneous packaging approaches, it is important to densely integrate all fluid flow paths into the device; volumetric heat dissipation emerges as a performance metric in this new heat sinking paradigm. In this paper, a compact hierarchical manifold microchannel design is presented that utilizes an integrated multilevel manifold distributor to feed coolant to an array of microchannel heat sinks. The flow features in the manifold layers and microchannels are fabricated in silicon wafers using deep reactive-ion etching. The heat source is simulated via Joule heating using thin-film platinum heaters. The on-chip spatial temperature measurements are made using four-wire resistance temperature detectors. The individual manifold layers and the microchannel-bearing wafers are diced and bonded into a sealed stack via thermocompression bonding using gold layers at the mating surfaces. Thermal and hydrodynamic testing is performed by pumping the dielectric fluid HFE-7100 through the device at a known flow rate, temperature, and pressure at different levels of chip heat input. A volumetric heat density of up to 2870 W/cm3 is dissipated at a chip temperature less than 112 °C and microchannel pressure drop less than 27 kPa. The overall pressure drop is governed by flowing through the manifold, rather than the microchannels, in this compact heat sink that occupies envelope of 5 mm $\times 5$ mm $\times2.3$ mm including all the functional flow features.

A hierarchical manifold microchannel heat sink array is fabricated and experimentally characterized for uniform heat flux dissipation over a footprint area of 5 mm x 5 mm. A 3 x 3 array of heat sinks is fabricated into the silicon substrate containing the heaters for direct intrachip cooling, eliminating the thermal resistances typically associated with the attachment of a separate heat sink. The heat sinks are fed in parallel using a hierarchical manifold distributor that delivers flow to each of the heat sinks. Each heat sink contains a bank of high-aspect-ratio microchannels; five different channel geometries with nominal widths of 15 mu m and 33 um and nominal depths between 150 mu M and 470 mu m are tested. The thermal and hydraulic performance of each heat sink array geometry is evaluated using HFE-7100 as the working fluid, for mass fluxes ranging from 600 kg/m(2) s to 2100 kg/m(2) s at a constant inlet temperature of 59 degrees C. To simulate heat generation from electronics devices, a uniform background heat flux is generated with thin-film serpentine heaters fabricated on the silicon substrate opposite the channels; temperature sensors placed across the substrate provide spatially resolved surface temperature measurements. Experiments are also conducted with simultaneous background and hotspot heat generation; the hotspot heat flux is produced by a discrete 200 mu m x 200 mu m hotspot heater. Heat fluxes up to 1020 W/cm(2) are dissipated under uniform heating conditions at chip temperatures less than 69 degrees C above the fluid inlet and at pressure drops less than 120 kPa. Heat sinks with wider channels yield higher wetted-area heat transfer coefficients, but not necessarily the lowest thermal resistance; for a fixed channel depth, samples with narrower channels have increased total wetted areas owing to the smaller fin pitches. During simultaneous background and hotspot heating conditions, background heat fluxes up to 900 W/cm(2) and hotspot fluxes up to 2700 W/cm(2) are dissipated. The hotspot temperature increases linearly with hotspot heat flux; at hotspot heat fluxes of 2700 W/cm(2), the hotspot experiences a temperature rise of 16 degrees C above the average chip temperature. (C) 2018 Elsevier Ltd. All rights reserved.

High-heat-flux removal is necessary for next-generation microelectronic systems to operate more reliably and efficiently. Extremely high heat removal rates are achieved in this work using a hierarchical manifold microchannel heat sink array. The microchannels are imbedded directly into the heated substrate to reduce the parasitic thermal resistances due to contact and conduction resistances. Discretizing the chip footprint area into multiple smaller heat sink elements with high-aspect-ratio microchannels ensures shortened effective fluid flow lengths. Phase change of high fluid mass fluxes can thus be accommodated in micron-scale channels while keeping pressure drops low compared to traditional, microchannel heat sinks. A thermal test vehicle, with all flow distribution components heterogeneously integrated, is fabricated to demonstrate this enhanced thermal and hydraulic performance. The 5 mm x 5 mm silicon chip area, with resistive heaters and local temperature sensors fabricated directly on the opposite face, is cooled by a 3 x 3 array of microchannel heat sinks that are fed with coolant using a hierarchical manifold distributor. Using the engineered dielectric liquid HFE-7100 as the working fluid, experimental results are presented for channel mass fluxes of 1300, 2100, and 2900 kg/m(2) s and channel cross sections with nominal widths of 15 mu m and nominal depths of 35 mu m, 150 mu m, and 300 mu m. Maximum heat flux dissipation is shown to increase with mass flux and channel depth and the heat sink with 15 mu m x 300 mu m channels is shown to dissipate base heat fluxes up to 910 W/cm(2) at pressure drops of less than 162 kPa and chip temperature rise under 47 degrees C relative to the fluid inlet temperature. (C) 2017 Elsevier Ltd. All rights reserved.

In this study, the thermal performance of two commercially available vortex tubes was investigated by measuring inlet and outlet pressures, temperatures, and flow rates. A variety of vortex generators, each with a unique combination of fin height and cold stream diameter, were tested for each vortex tube. Experiments were conducted over a wide range of inlet pressures and cold fractions. Decreasing the cold fraction was found to decrease the cold stream temperature while also decreasing the cold stream flow rate. For each vortex generator, there is an optimal cold fraction that provides the maximum cold stream cooling potential. A clear relationship between maximum cooling potential and fin height or cold stream diameter is not apparent.

This work focuses on the fabrication and experimental characterization of a two-phase hierarchical manifold microchannel heat sink array for intrachip high-heat-flux dissipation. A test device with a 5 mm × 5 mm heated area and 9 × 9 array of heat sinks, each with 18 parallel channels (19 μm × 155 μm), is fabricated in silicon. A multi-layer hierarchical manifold fabricated in silicon is bonded to the heat sink array. Flow boiling experiments are conducted using HFE-7100 as the working fluid at mass fluxes of 200 kg/m 2 s and 300 kg/m 2 s. The test device is able to dissipate heat fluxes up to 445 W/cm 2 at a chip temperature of less than 40 °C above the fluid and at a pressure drop less than 80 kPa. A maximum heat transfer coefficient of 31,900 W/m 2 K occurred at a mass flux of 300 kg/m 2 s and a heat flux of 301 W/cm 2 . The effects of heat flux on chip temperature, heat transfer coefficient, and pressure drop are investigated.

A hierarchical manifold microchannel heat sink is used to dissipate heat from a small hotspot region superposed on a larger region of uniform background heat flux. A 5 mm × 5 mm overall chip footprint area is cooled using a 3 × 3 array of intrachip silicon microchannel heat sinks fed in parallel using a manifold distributor. Each heat sink consists of a bank of 25 high-aspect-ratio microchannels that are nominally 30 μm wide and 300 μm deep. The uniform background heat flux is generated with a 3 × 3 array of thin-film heaters fabricated on the chip; temperature sensors placed in each of these nine heating zones provide spatially resolved chip surface temperature measurements. An individually powered 200 μm × 200 μm hotspot heater is centered on the chip. The heat sink thermal and hydraulic performance is evaluated using HFE-7100 as the working fluid and for mass fluxes ranging from 600 kg/m2s to 2070 kg/m2s at a constant inlet temperature of 60°C and outlet pressure of 122 kPa. Background heat fluxes up to 450 W/cm2 and hotspot fluxes of greater than 2500 W/cm2 are simultaneously dissipated. The chip temperature uniformity and maximum temperature rise during hotspot heating are assessed. For the case with the highest simultaneous background and hotspot heat fluxes, the measured heat sink pressure drop is ~75 kPa and the average chip temperature is ~30°C above the fluid inlet temperature.

This chapter contains sections titled: Introduction Method Results Discussion and Conclusions Acknowledgements