Image and signal processing workloads are widely deployed on Graphics Processing Units (GPUs) for high throughput and on Field-Programmable Gate Arrays (FPGAs) for hardware specialization and energy efficiency. Soft GPU overlays on FPGAs aim to combine these advantages, yet existing solutions often depend on fixed hard processors or impose platform constraints that limit portability. This work extends a popular open-source soft GPGPU overlay to integrate a soft RISC-V control plane and enable compatibility with High-Bandwidth Memory (HBM2). The resulting system can be instantiated on FPGA boards without a hard ARM processor, improving portability, simplifying system integration, and broadening deployability. Across representative image and signal processing kernels, the soft GPGPU achieves geometric-mean speedups of 114.60 & times; over a scalar soft RISC-V core and 19.72 & times; over a hard ARM core, demonstrating substantial performance benefits while retaining FPGA reconfigurability. HBM2 integration further benefits bandwidth-sensitive workloads by increasing sustained throughput and reducing the performance bottlenecks associated with off-chip memory access. Collectively, these results indicate that GPU-like programmability and performance can be delivered on reconfigurable platforms without reliance on hard CPU subsystems, providing a portable and scalable foundation for embedded vision and DSP acceleration.

Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow.

With the advent of advanced transmission technologies, powerful neural-network architectures, and the availability of cheap sensing solutions, new paradigms for monitoring, controlling, and optimizing any automated system are appearing. While traditionally, sensors simply provided visual or acoustic feedback to human operators of such systems, nowadays, autonomous systems more and more rely on the automatic sensing and processing of such data to react and adapt their control mechanisms. In such complex control systems, sensor networks play a vital role. In this paper, we assess the state of the art in the three main components used within sensor networks: smart sensing elements, transmission technologies, and processing technologies. Concerning the latter, more and more artificial intelligence-based methods are developed and applied turning smart sensor networks into intelligent or even cognitive sensor networks. For the development of such sensing systems, a high variety of performance metrics could be important to the designer. This paper discusses the vast design space for intelligent sensor networks and provides guidance and directions on how to construct future intelligent sensor networks efficiently.

With the advent of advanced transmission technologies, powerful neural-network architectures, and the availability of cheap sensing solutions, new paradigms for monitoring, controlling, and optimizing any automated system are appearing. While traditionally, sensors simply provided visual or acoustic feedback to human operators of such systems, nowadays, autonomous systems more and more rely on the automatic sensing and processing of such data to react and adapt their control mechanisms. In such complex control systems, sensor networks play a vital role. In this paper, we assess the state of the art in the three main components used within sensor networks: smart sensing elements, transmission technologies, and processing technologies. Concerning the latter, more and more artificial intelligence-based methods are developed and applied turning smart sensor networks into intelligent or even cognitive sensor networks. For the development of such sensing systems, a high variety of performance metrics could be important to the designer. This paper discusses the vast design space for intelligent sensor networks and provides guidance and directions on how to construct future intelligent sensor networks efficiently.

Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration.

Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms.

In this paper we consider the fundamental operations dilation and erosion of mathematical morphology. Many powerful image filtering operations are based on their combinations. We establish homomorphism between max-plus semi-ring of integers and subset of polynomials over the field of real numbers. This enables to reformulate the task of computing morphological dilation to that of computing sums and products of polynomials. Therefore, dilation and its dual operation erosion can be computed by convolution of discrete linear signals, which is efficiently accomplished using a Fast Fourier Transform technique. The novel method may deal with non-flat filters and incorporates no restrictions on shape or size of the structuring element, unlike many other fast methods in the field. In contrast to previous fast Fourier techniques it gives exact results and is not an approximation. The new method is in practice particularly suitable for filtering images with small tonal range or when employing large filter sizes. We explore the benefits by investigating an implementation on FPGA hardware. Several experiments demonstrate the exactness and efficiency of the proposed method.

Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs.

The ongoing megatrends in industry and academia like the Internet ofThings (IoT), the Industrial Internet of Things (IIoT) and Cyber-Physical Systems(CPS) present the developers of modern computer architectures with variouschallenges. A novel class of processors which provide more data throughputwith a simultaneously tremendously reduced energy consumption are required asa backbone for these “Things”. Additionally, the requirements of CPS like realtime, reliability, dependability, safety, and security are gaining in importance inthese applications. This paper shows a brief overview of novel processor architecturesproviding high flexibility to adapt during design- and runtime to changingrequirements of the application and the internal and external system status.

The research work presented in this paper is about a holistic tool-chain for generating, configuring and evaluating application-specific Coarse-Grained Reconfigurable Array (CRGA) architectures. This development was part of a large EU funded project with the name EXTRA. The reduced complexity of the architecture in comparison to fine-grained architectures like FPGAs is exploited to evaluate the Just-in-Time generation of VCGRA configurations. The manuscript presents the tool-chain that is responsible for the implementation of applications on the coarse-grained architecture. In particular, the tools for partitioning the applications, mapping the partitions and controlling the execution of the entire application on the target architecture will be examined. In addition, both the user interface and the interfaces between the components of the tool-chain are described. Subsequently, the presented tools are evaluated using a practical example and various metrics. We show, that the creation of configurations for the presented architectures can be carried out rapidly and therefore the generation of new configurations at run-time is feasible.

The work, presented in this paper has been carried out within an EU-funded project with the name EXTRA, aimed at creating an environment to generate, configure and evaluate user-customizable Coarse-Grained Reconfigurable Array (CGRA) architectures, called VCGRA. The tools provide a fully automatic development and evaluation platform for a VCGRA architecture including synthesis and execution of the VCGRA with its corresponding hardware configuration and the required interfaces on an FPGA platform. Furthermore, it also provides the necessary software modules for data transmission between the processing system (PS) and the VCGRA on reconfigurable hardware. In this paper, the part of the “VCGRA Toolflow” which is responsible to provide the generation of the VCGRA hardware’s FPGA-bitstream from a specification is discussed. Especially the generation of the VCGRA hardware, the automatic creation of the required interfaces and the evaluation of the improvements are presented. The toolflow is planned to be an open source project, providing hardware developers with a framework to create extensions for the VCGRA architecture, and to make them accessible for software developers. Many aspects of the hardware can be customized, including the functions provided by the Processing Elements and the communication infrastructure as well as the target platform integration. Furthermore, software developers from the EDA domain are enabled to provide, integrate and evaluate algorithms for application mapping.

Coarse-grained reconfigurable hardware reduces reconfiguration effort in terms of bitstream-length and synthesis time, since the configuration-bits target a set of wires or a processing units functionality instead of single connections and LUT-entries. Therefore logic-synthesis can be reduced to mapping and scheduling. In this paper we present a CGRA Tool Flow to (semi-)automatically create VCGRA architectures for numerical computations and the corresponding configurations for these architectures. In our example we achieved run-time reconfiguration times of around 6.5 μ s. To additionally reduce area consumption we evaluated the TLUT/TCON tool flow from the University of Ghent as a backend-tool for implementation. Results show up to 75