Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

We propose in this paper a reduction in the size of wearable antennas on silicon (Si) for medicinal frameworks and Internet of things (IoT) in various nanoapplications. This research also introduces one more type of dynamic patch antenna designed in favor of speech-enhanced healthcare applications. The most significant impediment to the adoption of smart correspondence and medical services frameworks is voice-enabled IoT. The primary objective of a body area network (BAN) is to give ceaselessly clinical information to the doctors. Actually, wireless body area network is flexible, dense, trivial, and less expensive. On the other hand, the main disadvantage is low efficiency for small printed antenna. Microstrip silicon antenna recurrence is changed because of ecological conditions, distinctive reception apparatus areas, and diverse framework activity modes. By using tunable antenna, the efficiency of bandwidth usage can be increased. Amplifiers are associated with the feed line of antenna in order to build its dynamic range. In this study, a dynamic polarized antenna is constructed, analysed, and attempted for fabrication. The gain of the antenna is 13 ± 2   dB for the frequency range of 390 to 610 MHz. The output of the polarized antenna is roughly 19 dBm. At different environmental conditions, the performance and ability to control the antenna could vary. To achieve stable performance, we have used varactor diode and voltage-controlled diode. This silicon wearable antenna can be fabricated and tested for many medical applications like health monitoring system and pacemakers. Furthermore, micromachining techniques can be used to lower the practical dielectric constant of silicon and hence improve radiation efficiency.

Modern transistors have two metallurgical junctions, one at the source/channel region and the other at the drain/channel region. A strong doping profile at these junctions is required to scale semiconductor devices below 10 nm. Considering all possible attempts to improve gadget attributes. Junctionless MOSFETs, FinFETs, and Tunnel FETs are all examples of non-classical semiconductor devices that use this principle. Junctionless FinFETs reduce short channel effects and improve ION/IOFF. However, in Junctionless FinFETs, ON current and ION/IOFF ratio are trade-offs. To overcome this problem, Gaussian doping was added into Junctionless FinFETs. Thus, combining Gaussian doping and junctionless FinFETs improves electrical properties and alleviates MOSFET problems. Thus, physics-based analytical modelling is essential to comprehend device behavior. This work focuses on Gaussian Doped Junctionless FinFETs for CMOS. This section compares the features of various doping configurations in Junctionless FinFETs. Bulk substrate Junctionless FinFETs can be doped uniformly, Gaussian uniformly, or graded uniformly (GRJL- FinFETs). To compare device Id-Vs, the first segment examined device Fin width, Fin height, channel length, oxide thickness, dielectric constant, and temperature.

Advances in microelectronics have enabled smaller technical nodes, lower threshold voltages, and greater working frequencies. Even though VLSI circuit performance and power consumption have improved as a result, the reliability of the designs has suffered. A fall in noise resistance and an increase in uncertainty from multiple sources of variability make circuits more vulnerable as technology scales down. Fault tolerant techniques are commonly used in safety-critical applications. Three-dimensional electrical devices like double gate, tri-gate, and nanowire field-effect transistors (FETs) give an alternative approach since they regulate the device channel better electrostatically. In this paper, a new form of FinFET with asymmetric gate and source/drain connections is developed, and its simulation results are shown. Asymmetric FinFETs exhibit better short-channel behavior when the current density is increased, according to the results of the benchmarking. High aspect ratio FinFETs give greater current per area while demanding significantly fewer horizontal geometry constraints, making them ideal for situations where conventional scaling has hit its physical limits. The suggested multigate FinFET provides improved performance in low-power and high-frequency applications, according to the experimental results. The work report also includes an evaluation of the proposed multigate FinFET’s dependability.