A communication system is simulated to explore bit error rate (BER) performance against different communication schemes and also changes in parameters controlling the constituent components in a communication system. Simulations are often performed in a digital computer using a simulation environment or directly programming in C or Fortran. With error rates down to 10/sup -12/ simulation times can be prohibitively long and with the new forward error correcting (FEC) codes BERs down to 10/sup -17/ could be considered. This paper describes an environment, which significantly reduces simulation times. It is based on a platform that utilizes field programmable gate array (FPGA) technology. FPGAs can be programmed to carry out operations in parallel so all of the components in a communication link can be implemented directly. Also the speed of operation of FPGAs are such that most parts Of the link can be operated in real time. In some applications faster than real time may be possible. The FPGA type of environment also provides convenient interfaces to the real world. Therefore real parts of a communication system can be easily added and provide "in-situ" simulations. Also direct comparisons can be made with the totally simulated counterpart. The paper presents a typical application concentrating on one component of a communication system. In this case, a convolutional encoder and Viterbi decoder. The information to be transmitted is simulated using a pseudo random noise generator core in the FPGA. Different distributions of noise are added to the link in appropriate places to simulate real noise effects and the demodulated, decoded output of the communication channel is compared with the original input. Speed-ups of several orders of magnitude can be realized with this system and runs taking days may be reduced to just several seconds of operation.

New computing architectures based on the DIME standard have been previously introduced which allow for processing of high frame rate imaging systems which may also need low latency capability, a common requirement for HWIL systems. This paper is presented in two sections: To achieve future realism in image generation systems for hardware-in-the-loop (HWIL) testing a significant increase in processing power is required, but additionally a suitable architecture is essential to provide low latency response on the data flow. Nallatech previously introduced DIME as a novel platform for HWIL systems which is capable of handling sub-frame latencies and greater than 100 Hz frame rates. We will demonstrate the system operating on traditional complex imaging problems, such as large convolution masks of 13 X 13 and also on new image generation techniques such as the particle method which is being developed by Matra British Aerospace Dynamics UK (MBDUK). MBDUK are proceeding on upgrading existing HWIL image generation systems for real-time particle models, to higher frame rates and increased complexity. Using Nallatech's latest DIME based architectures, models containing thousands of individual particles can be created at frame rates over 100 Hz and a resolution of 1024 X 1024 oversampled 4 times. This is possible because particle models exhibit high levels of parallelism ideal for exploiting the architecture of an FPGA. This paper will demonstrate the versatility of these particle models to create highly realistic signatures in terms of spatial dynamics and IR signature. Particle models are ideal for simulating dynamic objects such as flares, exhaust plumes, fires and explosions.

Synthetic scene generation systems require huge computational resources to operate on potentially large data sets of information and to interface to advanced sensor technology via current scene projectors. Nallatech Ltd has been focused in the area of low latency hardware and algorithm development for many years. In collaboration with Matra British Aerospace Dynamics UK, minimum latency systems have already been developed offering latency of only several video lines in 3D target scene generation systems. The rapid progression of FPGAs towards 1 million gate devices together with the ever increasing performance of today's DSPs have allowed Nallatech to formulate an architecture that is particularly suited to HWIL systems.

This paper describes the techniques which have been developed for an infra-red (IR) target, countermeasure and background image generation system working in real time for HWIL and Trial Proving applications. Operation is in the 3 to 5 and 8 to 14 micron bands. The system may be used to drive a scene projector (otherwise known as a thermal picture synthesizer) or for direct injection into equipment under test. The provision of realistic IR target and countermeasure trajectories and signatures, within representative backgrounds, enables the full performance envelope of a missile system to be evaluated. It also enables an operational weapon system to be proven in a trials environment without compromising safety. The most significant technique developed has been that of line by line synthesis. This minimizes the processing delays to the equivalent of 1.5 frames from input of target and sightline positions to the completion of an output image scan. Using this technique a scene generator has been produced for full closed loop HWIL performance analysis for the development of an air to air missile system. Performance of the synthesis system is as follows: 256 * 256 pixels per frame; 350 target polygons per frame; 100 Hz frame rate; and Gouraud shading, simple reflections, variable geometry targets and atmospheric scaling. A system using a similar technique has also bee used for direct insertion into the video path of a ground to air weapon system in live firing trials. This has provided realistic targets without degrading the closed loop performance. Delay of the modified video signal has been kept to less than 5 lines. The technique has been developed using a combination of 4 high speed Intel i860 RISC processors in parallel with the 4000 series XILINX field programmable gate arrays (FPGA). Start and end conditions for each line of target pixels are prepared and ordered in the I860. The merging with background pixels and output shading and scaling is then carried out in the FPGA's on a line by line basis. The whole process is carried out at 4 * 4 super-sampled rates to minimize spatial aliasing. Other techniques such as real time selective image filtering will be described and a video will be shown to demonstrate the successful application of these in HWIL and Trials proving.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.