Hot carrier gate current is one of the factors that influence the power and reliability of metal-oxide-semiconductor field effect transistor (MOSFET). Based on the physical process of generation of the hot carrier effect, a model of hot carrier gate current for uniaxially strained Si NMOSFET is developed. With that model, the simulation results of hot carrier gate current against stress intensity, gate-source bias, channel doping concentration, and drain-source bias are obtained and analyzed. The relationship between life time of time-dependent dielectric break down (TDDB) and gate-source bias is simulated and analyzed. Results show that the uniaxially strained Si MOSFET not only has smaller hot carrier gate current, but also has more stable reliability as compared with the strainless bulk device. Meanwhile, the simulation results match the experimental results very well, which validates the accuracy of the model.

The capacitance model is fundamental for the transient analysis, AC analysis and noise analysis of uniaxially strained Si MOSFET device and circuit. Firstly, the 16-differential capacitance model for uniaxially strained Si NMOSFET is developed. Secondly, the simulation results from that model match the experimental results well, which validates the accuracy of the model. Meanwhile the simulated relations of key gate capacitance Cgg to stress intensity, bias voltage, channel length and concentration of poly gate are obtained and analyzed, showing that the value of Cgg is a little larger than that of strainless bulk device while the changing tendency keeps the same.

Based on the structure of strained Si/SiGe NMOSFET, a unified charge model is presented, in which charge conservation is guaranteed by using the charge as the state variable. The model describes device characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions using a smoothing function, and guarantees the continuities of charges and capacitances. Furthermore, capacitance models have been presented using Verilog-A, a language to describe analog behavior. Comparisons between the model and measured data show that the charge model can describe the device characteristics well. The proposed model is useful for the design and simulation of integrated circuits made of strained Si.

The Bit-Plane Encoder (BPE) is the key part of CCSDS-IDC that encodes the coefficients of 2-D Discrete Wavelet Transform (DWT). In common sense, it is considered as the bottleneck of throughput performance and hardware resource consumption. An efficient VLSI architecture of BPE implemented with parallel and pipeline technology is proposed in this paper. In this architecture, the whole bit planes of each DWT coefficient could be encoded simultaneously and pipeline is utilized in three functional parts of the bit plane coding. The proposed architecture has been implemented in a Xilinx FPGA, its throughput could be improved three times while its resource consumption is only about a quarter comparing with the published architectures.