This paper presents a decentralized control algorithm for interleaved converters for high reliability application.In previous literature, a master control provides information on the system configuration in order to generate the different carriers.The whole premise of the proposed algorithm is that each module only communicates with its two immediate neighbors which reduce communication latency.Using only the neighbors proper interleaving of the carriers and balancing the converter leg currents is achieved.Carriers from each converter automatically adjust their phase, as modules are added or removed dynamically.Such implementation offers a completely decentralized control which makes it fully modular.Results of the controller are presented using a real-time simulator.

The modular multilevel converter (MMC) has been widely adopted in different applications, such as high-voltage direct current (HVDC), electric drives and static synchronous compensators. Despite the application, MMC realization requires a high number of power electronic components, sensors, and communication cables. This paper proposes a sliding-mode observer for capacitor voltages of the MMC, using the measurements of arm currents and arm voltages. A linear corrector within the hysteresis band is proposed to reduce the chattering in the observer dynamics. Moreover, guidelines for tuning the observer gain are presented. The SM capacitance value is included as a parameter uncertainty of the observer. The proposal reduces the requirements of voltage sensors and optical links in MMC and allows fault-tolerant operation. The proposed observer performance is evaluated through a simulation of 100 MVA three-phase MMC-HVDC during initialization, steady-state, and submodule failures. The effect of the switching and sampling frequencies on the observer performance is also evaluated. Finally, experimental results validate the proposal in a downscale 3 kVA single-phase MMC prototype.

The ongoing transition towards electrified transportation results in the increasing utilization of resonant converters with relatively high switching frequencies. Hardware-in-the-Loop testing plays an important role in the design and validation process of novel converter topologies and controllers. This paper addresses the challenges related to achieving a high degree of simulation fidelity of resonant converters for a hybrid electric aircraft application. An FPGA-based real-time simulation with oversampling of switching signals and high-order numerical integration method is proposed. A high degree of simulation fidelity of the overall DC-DC converter system, a hybrid DC-DC converter consisting of CLLC and LLC converters, is achieved.

Smart Transformers (STs) have a key role to play in establishing hybrid ac/dc grids. This paper focuses on challenges in ensuring high-fidelity Real-Time Simulation (RTS) of switching models of STs, in particular on the RTS of a switching model of the Dual-Active Bridge (DAB) converter utilized for the dc/dc power conversion stage. Phase-shifted modulation used for the operation of DAB converters requires a relatively small simulation time-step to achieve a sufficient level of simulation fidelity. An analytical condition for the upper limit of the simulation time-step required to achieve a predefined level of simulation fidelity for a given switching frequency and operating range of the phase-shift angle of a single-phase DAB converter is introduced in this paper. However, the size of the simulation time-step must be sufficiently large to allow the calculation of the switching model of the entire power-converter system in real time, which might be in conflict with the requirement in terms of simulation fidelity. In this case, a method of oversampling the switching signals is proposed, which allows for the utilization of a simulation time-step feasible for real-time model calculation while sampling switching signals at a rate higher than the simulation time-step. Using the approaches mentioned above, the paper provides validation of the simulation fidelity of RTS of switching models of DAB converters in open-loop operation and closed-loop operation with controlled output voltage.

LLC converters are a very commonly used topology in electric vehicles and in electric aircrafts, because of their high energy density, high efficiency due to natural zero-voltage-switching (ZVS) capabilities, and operation at a voltage gain less than, equal to or more than unity. This paper demonstrates a verification method of a designed resonant LLC converter using real-time hardware-in-the-loop simulation (HiL). The main advantage of this method is that a designed power converter can be tested and verified in real time prior to building a hardware prototype. This enables us to validate, debug and tune converter parameters without the experimental setup in a safe and hazard-free environment and with no risk of damage to expensive hardware. After a successful HiL simulation, it will be safe and cost-efficient to continue or implement the system in real hardware. However, real-time simulation of high-frequency LLC converters is very challenging due to the requirements for a very small simulation time step, even beyond hardware capabilities. In this paper, a 3.0 kW LLC converter is designed based on first harmonics approximation and time-domain simulation. Afterward, the designed converter is simulated in a real-time (RT) system equipped with an FPGA-based electrical solver that employs oversampling of switching signals. Finally, the results from the RT system are compared to experimental data from the hardware prototype to assess the performance of the simulation with respect to the actual results.

In power electronic, the goal is often to increase the power density and improve efficiency of a converter. Although this can be achieved with newer technologies such as multilevel converters, industries are known to be very conservative and often prefers older converter topology with improved components. Silicon carbide switches can increase switching frequency of converters, making it possible to achieve a higher power density and efficiency of a converter. Increasing PWM frequency also raise new challenges during design and validation of the converter due to limitations of real-time simulator sampling. This paper presents a new real-time simulator implementation solving the issue of power switches gating signal sampling, as well as the discretization of extremely small time-constant for real-time applications. The proposed simulation tool is validated against an offline simulation of a three-phase interleaved-boost converter operated at 169.25 kHz.

Silicon-carbide based, multi-level converters with dual-active-bridge (DAB) are getting attention for medium voltage, direct grid-connected, utility-scale photovoltaic (PV) applications due to their higher efficiency and power density. To de-risk complex control development for these high-voltage and high-power inverters, hardware-in-the-loop techniques are often required. Due to the high switching frequency and the large number of power electronic switches, off-the-shelf, real-time simulation tools are not yet fully developed for this application, even with FPGA-based simulators. To address this, a new co-simulation approach in FPGA is presented that utilizes Time-Stamped Bridge (TSB) for the higher frequency converters along with detailed fixed conductance based discrete device simulation of the rest of the circuit. A complex DAB-based PV converter with maximum switching frequency of 50 kHz is successfully simulated in real-time in the FPGA and the results are compared with offline simulation results. A controller hardware-in-the-loop (CHIL) platform is developed to demonstrate real-time, closed-loop test results for this DAB-based PV converter.

This paper proposes a model of a three-stage synchronous generator found in passenger aircrafts for hardware-in-the-loop (HIL) testing. The system includes two salient-pole synchronous machines, one permanent magnet synchronous machine (PMSM) with their respective resolvers, and encoders models, as well as two full-wave six-pulse AC-DC diode bridge rectifier and one DC-DC buck converter. The efficient combination of pipeline and parallel FPGA hardware design makes it possible to fit the model on a Xilinx Virtex 7 FPGA. The OP5607 real-time simulator of Opal-RT Technologies is used, and simulation time step as low as 250ns is achieved. Three scenarios are investigated understudied: balanced load change, unbalanced load change, and single-phase short-circuit fault, which are validated by Simscape/Power System library of Matlab/Simulink.

Multiphase machines are gaining popularity in clean, reliable and affordable energy systems for their robustness, reliability and fault-tolerant behavior. This paper addresses the problem of parameters estimation and the problem of controlling the currents of an asymmetrical six-phase induction machine with unmeasurable rotor currents. On one hand, this work proposes the use of recursive least squares estimation method that is effective and simple and allows fast convergence of the parameters to their real values. On the other hand, this paper proposes an augmented super-twisting algorithm that allows high tracking accuracy, fast finite-time convergence, matched and mismatched uncertainties rejection. Hardware-in-the-loop simulations have been conducted to demonstrate the performance and the efficiency of the estimation method and the developed nonlinear controller for the considered system.

In this study, a new control method dedicated to modular multilevel converters (MMCs) is proposed. The approach is based on local communication between the individual controls of each submodule (SM). The local values of the capacitor voltages and the carrier-phase angles are shared between immediate neighbours achieving balancing of their capacitor voltages, and an automatic interleaving of the pulse-width modulation (PWM) signals. Using an inter-cell communication strategy, the number of required data exchanges with a centralised controller is greatly reduced. This method works for any number of SMs present in the converter and provides an integrated dynamic reconfiguration capability to enable or disable SMs during operation, without any additional consideration for the control-algorithm's implementation. Such a capability is not offered by classical MMC control methods using either PWM or nearest-level control strategies. Higher stability, robustness and larger bandwidth of the proposed method are first demonstrated through real-time simulation. The auto-interleaving of the PWM carriers and the capacitor-voltage balancing, provide fast responses and adequate accuracy. Experimental results are provided using a 600V/3kW/18 cells single-phase MMC demonstrator confirming the simulation results, and the advantages of this SM control strategy.

In this paper a single-phase transformer-less hybrid series active filter (THSeAF) based on duo-neutral-point-clamped (D-NPC) converter to address distribution level power quality is proposed to investigate experimentally the efficiency of the hardware-in-the-loop (HIL) implementation for power electronics applications. This benchmark contributes to demonstrating the capability and efficiency of such real-time implementation for smart grid power quality (PQ) analysis which requires fast switching process with small sampling time. Such applications require the compensator to address major power quality issues related to a nonlinear load. This compensator presents an efficient and reliable solution for future grid applications to overcome voltage and current related issues as well as assisting the integration of renewables for a sustainable supply. The controller extracts voltage and current harmonics to be compensated. A proportional and resonant (P + R) regulator produces switching signals for the D-NPC converter. The paper demonstrates the reliability of the HIL simulation for power electronic applications assessing power quality related issues where a wide range of switching frequency is under study. A combination of simulation and real-time results are carried out to validate the performance and viability of the HIL implementation.

This paper presents a Multi FPGA based solution for large power systems and Microgrids real-time simulation. The proposed platform allows control and protection devices to be designed and tested in virtual power system, before they can be implemented in a physical system. This solution promotes flexibility of operation with no risk of components failure under any contingency analysis. To demonstrate the effectiveness of the OPAL-RT platform, a large distribution network (DN) of 210 bus bars and a Microgrid (MG) are considered. The MG includes a solar panel and a battery energy storage system (BESS). The complete power system including the DN and MG is simulated using only two Kintex-7 FPGA boards. The controllers of the MG distributed energy resources (DER) are compiled and real time simulated using a 3.5 GHz Intel processor. The performance of this overall Processor-In-The-Loop application (PIL) is validated based on two criteria: 1) Evaluation of the results accuracy compared to the reference offline simulation under steady state and transient conditions. 2) Evaluation of the losses introduced by the power interface used to split the DN into two FPGA boards.

This paper presents an asymmetrical phase-domain synchronous machine model using sub-microsecond sampling time on FPGA. Previous literature has presented synchronous machine simulated on FPGA where all three phases are symmetrical, allowing a representation in the dq-domain, and reducing the complexity of the equations to be solved. When a fault occurs within the machine winding, the machine's parameters become asymmetrical, in which case, classical dq-domain representation is inaccurate. There are two innovations in the proposed method. First, a finer representation of the machine is used, and second, the FPGA implementation does not require to invert a matrix during discretiz ations. Results from the proposed model are validated by comparing the ones obtained using an offline simulation with a variable-step solver.

As HVDC based on voltage source converter (VSC) technology has already reached 350 kVdc voltage level, this paper examines the feasibility of connecting four voltage source converter (VSC) modules, each rated at 200 kVdc, in series to form a pole of UHVDC rated at 800 kVdc. Due to the series connection layouts, the individual DC bus voltage inequality exists when power reversal occurs. A detailed control solution with DC voltage compensation equalizer for the series connected VSC-UHVDC system is developed and presented. The operation feasibility of the proposed UHVDC system is verified via simulation studies under different conditions such as active power step changes, reactive power step changes, and power reversal.

Multi-rate (MR) simulation is necessary for a system which contains both large and small time constraints. In the traditional MR real-time simulation of MMC, only the MMC valves are implemented on FPGA with a small time-step, while the rest parts are implemented on central processing units (CPU) with a large time-step. This paper presents a fully FPGA based MR real-time simulation of two MMC terminals. The FPGAs are decoupled by the stubline, and are parallelly simulated. Each FPGA is assigned with one MMC terminal, and its time-step can be flexibly chosen. The decoupled FPGAs can run asynchronously with their own model, which only communicate via the stubline without the synchro between them. Thus, the real-time simulation of a multi-terminal MMC-HVDC grid can be easily achieved while the accuracy of the simulation is also guaranteed. The real-time simulation results of the proposed methodology are provided.

This paper introduces a new insertion index selection method to control a Back-to-Back Modular Multilevel Converter (MMC) laboratory platform. The test bench is based on a Power-Hardware-In-the-Loop (PHIL) setup constructed from two 6kVA, 3-phase, 10 cells per arm MMC systems connected in Back-to-Back configuration. The proposed insertion index selection method uses the arithmetic mean of available upper and lower arm voltages in a leg to generate insertion indices; unlike classical closed-loop methods which use the available arm voltage of each arm (i.e. sum of measured capacitor voltages in an arm). For this purpose, a detailed mathematical derivation of available arm voltage ripple equations is introduced. Furthermore, impact of the proposed insertion method on inserted arm voltages that drives input and output currents is thoroughly explored. No additional control loops for arm energy difference are required, as the proposed method inherently achieves arm energy stabilization. Nevertheless, the number of measured signals to be fed back to a high-level controller is reduced to half. The PHIL setup is formed of MMC-1 which emulates an AC grid and MMC-2 which is controlled as a grid tied converter. Analytical findings along with experimental results obtained from the Back-to-Back PHIL setup proves the effectiveness of the proposed method.

Modular multilevel converters (MMC) have been at the heart of numerous research projects and publications over the last decade. This topology is particularly challenging when it comes to real-time simulation; it has thousands of power-switching devices, control signals, and differential equations to solve. This has led to various models with different levels of detail. Although, all models are equally accurate, to some extent, it might not be required to use a fully detailed model depending on the objectives of the analysis. In this paper, five different MMC modelling techniques are studied for different number of submodules. Converter behaviour during initialization, normal operations and faulty conditions are investigated. The impact of the detail level of each model is reviewed for the different control loop of the converter, and also different faults applied to the converter.

Real-time simulation is an important tool of validating the performance of the modular multilevel converter (MMC). By using the field programmable gates array (FPGA), MMC valves with hundreds of sub-modules and the large number of inputs and outputs can be simulated in real-time. In the traditional FPGA based real-time simulation, only the MMC valves are implemented on FPGA, while the rest parts including AC or DC grids and inductors are implemented on CPU. However, the subsystem simulated on CPU has slower dynamics than the subsystem simulated on FPGA. There is a delay of CPU time-step between these two subsystems, which may affect the accuracy of the results especially under fault condition. This paper presents a real-time simulation of modular multilevel converters, and DC grids fully based FPGA with sub microseconds time-step. Benefitting from using the electric hardware solver (eHS), all the components including the MMC valves and DC grid system can be easily implemented on FPGA. Thus, the high-fidelity of the simulation is guaranteed. The results of the proposed FPGA based real-time simulation are provided.

This paper presents a new validation method to demonstrate the stability and accuracy of a discretized system by using multiple sampling rates. Such multirate simulations are often encountered in real-time simulation application, where large power systems are coupled with circuit containing power electronics devices. Multirate simulation should not be confused with variable-step simulation, which is a single-rate simulation type. In single-rate simulation, the discretized system is stable when its discrete poles are within the unitary circle. When using multirate solvers, state variables are discretized with different sampling rates and poles location analysis for the system's equations cannot be used. This paper introduces a formal mathematical analysis demonstrating stability of multirate real-time simulation. System state variables, regardless of their discretization time step, are found in a single matrix. Classical pole analyses are thereafter used to test stability with poles location analysis. The method is given in a generalized form, and can be applied to various multirate solvers. The proposed method was found accurate and reliable using numerical examples.

This paper proposes to observe a set of capacitor voltages from modular multilevel converter using only one current and one voltage measurement for the ensemble. This is achieved by estimating the voltage values using the current and the gating signal. The estimation is then corrected using a sliding mode control on the voltage error of the whole half-arm. When compared with previously proposed observers, this one has the advantage of being simpler and expandable to any number of submodules. Furthermore, each half-arm can be treated independently, making it possible to solve them in parallel. Accuracy of the proposed observer is demonstrated through a real-time simulation of a 300 submodules three-phase modular multilevel converter during initialization, steady-state and AC-fault operation.