A multilayer SiN barrier film with high breakdown field and low leakage current is developed for Cu low-k interconnects and is compared with the SiCNH barrier film used in previous technology nodes. Ultrathin SiN barrier cap films also provide high conformality and fill recessions in Cu lines as observed after CMP. The conformal ultrathin (8-14 nm) multilayer SiN cap is robust with higher breakdown field, lower leakage and forms a good oxidation barrier. The electromigration activation energy for a SiN cap layer of 10-12 nm dielectric thickness is about 0.9 eV.

We demonstrated a self-aligned two-step reactive ion etching (RIE) process to pattern high density magnetic tunnel junction (MTJ) arrays. We did the RIE for the top electrode (TE) and stop in the middle of the tunnel barrier. A nitride conformal film was coated on the device pillars as a dielectric spacer. The conformal spacer protects the tunnel barrier from shorting by redeposition and provides a mask for the bottom electrode (BE) RIE. We used this process and completed perpendicular MTJ devices with our process flow. We tested the devices by measuring magnetic field switching and spin transfer torque switching. We get tunneling magnetoresistance (TMR) up to 100%, switching current as low as 60 μA at 100 ns, switching current density Jc0 as low as 2.5 × 106 A/cm2 and endurance above 109 for devices as small as 50 nm in diameter. The results are compared with devices from a TE RIE only process, and we find minimum damage was made by the BE RIE. We also discuss the size dependence of MTJ parameters such as TMR and free layer coercive field and offset field, which is very related to the RIE process.

Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

A new boron-based hardmask material was developed using a conventional CVD approach to address the integration challenges associated with the use of metal hardmask for low k dielectric patterning. Its low and tunable stress eliminates any patterning concerns due to line bending for device nodes below 20nm. Defectivity is also reduced because by-products from its F-based etch (BFx) are volatile unlike TiFx based defects, which dramatically widens the manufacturing process window. Extensive study concludes that boron content can be optimized to achieve good etch selectivity to the porous low k oxide. Preliminary electrical test using 45nm node 2-metal level structure showed good yield and 9% RC reduction compared to the conventional tri-layer integration scheme