A multi-standard direct conversion receiver achieves 2.2dB NF at 6GHz with a 15kHz flicker noise corner. 1dB RF bandwidth is 4.9-6GHz, power dissipation is 56mW from 1.3V and active die area is less than 1.2mm(2), including the input matching network In-band P1dB and IIP3 at maximum gain (39dB) are -30dBm and -18dBm, respectively, and three gain steps of 6dB are provided. DC offset from self mixing is less than 10mv.

In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15m\V; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 m\V.

A novel low power architecture and integrated circuit is presented for applications in the analog baseband processing section of next generation wideband direct conversion wireless receivers. The proposed system features current mode signal processing for filtering and analog to digital conversion as well as large programmable gain to handle the large signal variations present in wireless designs. The use of current mode signal processing allows low voltage and low power operation and addresses the design concerns in modem mobile terminals that aim to reduce energy consumption for enhanced battery life. An experimental circuit that demonstrates the feasibility of designing such a system consumes only 5 mW of power at 1.5 V with an input dynamic range of 60 dB, a noise figure of 25 dB and linearity better than + 1 dBm at maximum gain setting in SiGe technology.

A passive noise suppression technique was implemented on a family of monolithic low-noise amplifiers using a 0.5mum SiGe BiCMOS process with 47GHz fT transistors. This method provides the entire circuit with a conductive path to ground the P-substrate. Near active device regions, noise injection and crosstalk paths are shunted to ground. This technique decreased the LNAs noise figures by 1.88dB, 0.34dB, and 0.82dB at 5.25GHz, 2.45GHz, and 2.14GHz respectively. While DC power consumption is reduced, the gain improved by 5.3dB and 2.5dB at 5.25GHz and 2.14GHz respectively

In this paper, the design and measured results of an active double-balanced direct down-conversion mixer at 18 GHz is presented. The mixer, which is fabricated in IBM's 45-GHz f/sub t/ SiGe BiCMOS process achieves a 4.5 dB conversion gain, a 7.1 dB double sideband noise figure, an IIP/sub 3/ of -1 dBm, an IIP/sub 2/ of 20.3 dBm, and a l-dB compression point at 12.2 dBm output power. The mixer DC power consumption is 16.5 mW with a 3.3 V supply. To the authors' knowledge, the design achieves the highest figure of merit among published direct down-conversion mixers operating at similar frequencies in comparable Si-based process.

A 37-GHz voltage controlled oscillator (VCO) fabricated in IBM's 47-GHz SiGe BiCMOS technology is presented. The VCO achieves a phase noise of -81dBc/Hz at 1-MHz offset from the carrier while delivering an output power of -30dBm to 50 /spl Omega/ buffers. Drawing 15-mA of dc current from a 3-V power supply the VCO occupies 350μm×280μm of silicon area. Capacitive emitter degeneration and compact layout are used to achieve high f/sub OSC//f T ratio.

A 37-GHz voltage controlled oscillator (VCO) fabricated in IBM's 47-GHz SiGe BiCMOS technology is presented. The VCO achieves a phase noise of -81 dBc/Hz at 1-MHz offset from the carrier while delivering an output power of -30 dBm to 50 Omega buffers. Drawing 15-mA of dc current from a 3-V power supply the VCO occupies 350 mum x 280 mum of silicon area; Capacitive emitter degeneration and compact layout are used to achieve high f(OSC)/ f(T) ratio.

An injection-locked clock recovery (CR) unit capable of extracting the clock from random binary sequences is presented. At 2.3V, the clock recovery circuit consumes only 14.3mW and correctly recovers a 10.3GHz clock from a 2(boolean AND 31)-1 PRBS data stream. The active chip area is 0.35mm x 0.37mm.

An injection-locked clock recovery (CR) unit capable of extracting the clock from random binary sequences is presented. At 2.3V, the clock recovery circuit consumes only 14.3mW and correctly recovers a 10.3GHz clock from a 2/sup 31/ - 1 PRBS data stream. The active chip area is 0.35mm /spl times/ 0.37mm.

A single-chip implementation of a variable supply voltage power amplifier (PA) is presented. The circuit is design in SiGe BiCMOS technology and is composed of a differential power amplifier designed for WCDMA operation and a "buck" DC-DC converter. The combined system varies the supply voltage of the PA from 2.7 V to 1.2 V and maintains system linearity while the output power is not at its maximum. The system achieves an average battery current reduction of 30% and an average efficiency improvement of 46% compared to a fixed supply voltage approach, while occupying a 2 mm /spl times/ 2.5 mm die area.

We present a 10.3Gb/s full-rate fully integrated injection-locked CDR circuit with a BER lower than 1e-12 over a 160MHz lock range. With a 33V supply, the CDR core and the output buffers consume 230mW and 175mW, respectively, while occupying an active area of 730mum times 680mum. The CDR is fabricated in a mature 45-GHz fT SiGe BiCMOS technology

A low noise amplifier (LNA) in 0.13 mu m CMOS for ultra-wideband (UWB) front-ends is presented. The LNA has a peak gain of 11.3 dB and a 3.0 - 10.7 GHz -3 dB bandwidth. Its broadband matching is better than -10 dB for S11 and -15 dB for S22. Its lowest noise figure (NF) is 2.2 dB and the average NIP is 3 dB. The LNA achieves NFmin performance over the entire bandwidth by using a power-constrained simultaneous noise and input matching concept. It consumes only 4.8mW with a 1.2 V supply for the amplifier core and 1.6 mW in the output buffer. A comparison with recently published UWB LNA's shows this design has the best overall performance among both CMOS and SiGe designs.