This paper presents a 25.6 Gbit s −1 high-speed transmitter (HST) manufactured using 28nm CMOS technology. The HST macro-block includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100Ω line as well as a silicon photonics (SiPh) ring modulator (RM). The design adopts various radiation hardening techniques, such as triple modular redundancy (TMR), physical circuit spacing, and protection against radiation-induced leakage. The circuit achieves a total ionizing dose (TID) tolerance above 1 Grad, which aligns with the future large hadron colider (LHC) detector upgrade requirements. In this paper, the architecture of the HST based on the LC tank-based ADPLL, half-rate serializer, and the source-series-terminated (SST) output driver included in the prototype chip is described. The experimental results are reported, including general evaluation as well as the radiation characterization of the HST.

Ongoing developments in the field of radiation-tolerant high-speed transmitters (HSTs) aim at increasing the data rates above 25 Gb/s while increasing total ionizing dose (TID) tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causes duty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates for process voltage temperature (PVT) variations as well as radiation-induced duty-cycle distortion of the clock.

Pioneering physics experiments require increasingly faster data transfers and high-throughput electronics, which drives the research towards a new class of serialisers and optical links. In this framework, the DART28, a 100 Gbps radiation tolerant serialiser and driver, has been designed in 28 nm CMOS technology, submitted in April and delivered in August 2023. The development has been coupled with an FPGA based emulation, which provided an early assessment of its behaviour, a scalable system-level demonstrator and an effective evaluation tool for compatible commercial solutions. The challenges faced in this research and the architecture of both the hardware setup and the firmware will be described.

The paper presents the Dual Use Driver (DUDE) for high speed links, a circuit designed for the Demonstrator ASIC for Radiation -Tolerant Transmitter in 28 nm CMOS (DART28) developed under the EP -R&D programme on technologies for future high energy physics experiments. The driver operates at 25.6 Gbps and it allows driving both 100 omega transmission lines and optical Ring Modulators (RMs) integrated in a photonics integrated circuit (PIC). The driver includes configurable pre -emphasis. The device will allow to demonstrate the feasibility of wavelength division multiplexing (WDM) optical links operating with bandwidths in excess of 100 Gbps per fiber that are capable of sustaining total ionizing radiation doses up to 10 MGy.

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.