The complexity and functionality of mobile digital devices is continuously growing. This results in a higher energy consumption of such devices. To counteract this trend, it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. The generic design of this characterization system enables an easy portability to other architectures. For an accurate current measurement, a high-performance sampling technique has been established, which can be either clock or energy driven. The performance of those techniques is analyzed, and the advantages over the conventional solution of a series resistor are discussed. During the characterization of different processor platforms, it could be shown that the characterization effort can be reduced from three man-months to two man-weeks.

The complexity of mobile devices is continuously growing due to the increasing requirements on performance. In portable systems such as smart cards, not only performance is an important attribute, but also the power and energy consumed by a given application. It is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. Both the optimization and the characterization are carried out mostly manually and are thus very time consuming processes. This paper presents an environment for automated instruction set characterization, based on physical power measurements. Further, an optimization system is presented that allows an automated reduction of power peaks based on a compiler optimization.

The steadily increasing performance of RF-powered devices implies also a rise in power consumption. To counteract this trend, it is mandatory to accomplish power optimizations at every stage in the HW/SW co-design process. Since the momentarily available energy depends on the power profile of anterior tasks, the behavior of the RF-interface has to be considered in the optimization process to achieve a maximum of efficiency by maintaining the system stability.This paper introduces an accurate discrete-time model of the energy source of RF-powered devices. Based on this model, a power profile analysis tool has been developed, which identifies automatically critical regions for the energy source in the current profile of the system. The use of this framework is illustrated in a software optimization process, which intends to eliminate the detected critical areas.

This paper presents a HW/SW co-design methodology for the design of resource limited embedded devices. The design methodology takes advantage of system abstraction and attached vertical and horizontal co-design flows. The vertical co-design flow focuses on a system consisting of a standard processor and a custom hardware as co-processor. The horizontal co-design flow implements the system's functionality entirely in software, but the underlying processor is developed at the same time. The focus of the paper is on the detailed description of the two design flows under the aspect of power awareness.

In the design and optimization of power-aware computing systems, it is often desired to estimate power consumption at various levels of abstraction, e.g., at the transistor, gate, RTL, behavioral or transaction levels. Tools for power estimation at these different levels of abstraction require specialized expertise, e.g., understanding of device physics for circuit-level power estimation, and as such are necessarily developed by different research communities. In the optimization of complete platforms however, it is desired to be able to obtain aggregate power and performance estimates for the different components of a system, and this requires the ability to model the system at a mixture of levels of abstraction. One approach to enabling such cross-abstraction modeling, is to define a mechanism for interchange of data between tools at different layers of abstraction, for both static analysis and simulation-based studies. This document presents preliminary discussions on the requirements of such an interface.

In the design and optimization of power-aware computing systems, it is often desired to estimate power consumption at various levels of abstraction, e.g., at the transistor, gate, RTL, behavioral or transaction levels. Tools for power estimation at these different levels of abstraction require specialized expertise, e.g., understanding of device physics for circuit-level power estimation, and as such are necessarily developed by different research communities. In the optimization of complete platforms however, it is desired to be able to obtain aggregate power and performance estimates for the different components of a system, and this requires the ability to model the system at a mixture of levels of abstraction. One approach to enabling such cross-abstraction modeling, is to define a mechanism for interchange of data between tools at different layers of abstraction, for both static analysis and simulation-based studies. This document presents preliminary discussions on the requirements of such an interface.

RF-powered smart cards are widely used in different application areas today. The complexity and functionality of smart cards is growing continuously. This results in a higher power consumption. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability. If the power consumed by such a device exceeds the power provided by the RF-field a reset can be triggered by the power control unit or otherwise the chip may stay in an unpredictable state. Flattening the power profile can thus increase the stability of a system. We present an optimization system which intends to eliminate critical peaks after the analysis of the power profile of an executed application. In an iterative compile process an optimal tradeoff between power and performance has to be found. This is achieved by selecting or deselecting different optimization passes on the intermediate language level of the compiler.

NXP Semiconductors, Business Line Identi cation8101, Gratkorn, Mikronweg 1, Austriaulrich.neffe@nxp.comAbstract. The steadily increasing performance of mobile devices alsoimplies a rise in power consumption. To counteract this trend it is manda-tory to accomplish software power optimizations based on accurate powerconsumption models characterized for the processor. This paper presentsan environment for automated instruction set characterization based onphysical power measurements. Based on a detailed instruction set de-scription a testbench generator creates all needed test programs for acomplete characterization. Afterwards those programs are executed bythe processor and the energy consumption is measured. For an accurateenergy measurement a high performance sampling technique has beenestablished, which can be either clock or energy driven.Keywords. Software energy estimation, automated processor charac-terization, testbench generator, current measurement, clock driven sam-pling, energy driven sampling.

The complexity of embedded systems is continuously growing due to the increasing requirements on performance. In portable systems such as smart cards, not only performance is an important attribute, but also the power and energy consumed by a given application. Sources of energy used in smart card systems like batteries and electromagnetic fields are not such ideal elements, as their effectiveness depends heavily on the energy consumed over time. Optimization strategies proposed so far are implemented statically. Often a manual measurement of the current profile followed by manual optimizations is carried out. This procedure is very time consuming. We present a method for reducing automatically the power of an application based on a compiler optimization.

The steadily increasing performance of mobile devices implies also a rise in power consumption. To counteract this trend it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. For an accurate current measurement a high performance sampling technique has been established, which can be either clock or energy driven. The performance of those techniques is analyzed and the advantages over the conventional solution of a series resistor are discussed.

The complexity of mobile devices is continuously growing due to the increasing requirements on performance. In portable systems such as smart cards, not only performance is an important attribute, but also the power and energy consumed by a given application. It is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. Both the optimization and the characterization are carried out mostly manually and are thus very time consuming processes. This paper presents an environment for automated instruction set characterization, based on physical power measurements. Further, an optimization system is presented that allows an automated reduction of power consumption based on a compiler optimization.

RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed by a given application. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability and security. Flattening the power profile can thus increase the stability and security of a system. In this paper we present an optimization system that allows a reduction of power peaks based on a compiler optimization. The optimizations are done on different levels of the compiler. In the backend of the compiler we present new instruction scheduling algorithms. On the intermediate language level we propose the use of iterative compiling for reducing critical peaks.

Nowadays, there are strong movements towards development and usage of multimedia courseware as a means of knowledge transfer. Many authors of textbooks or lecture notes are now striving to redesign the supporting material for their major courses in a structured, highly efficient way, including interactive content and media. Thus, in order to avoid unnecessary work load resulting from updating and publishing various courseware versions, tools for improving document creation and conversion have been developed and are now being applied for the first time on a new “Electrodynamics”‐‐ courseware.