Wire bond technology for IC devices has been the backbone of the semiconductor industry for many years. The drive for fme pitch wire bonding is to reduce silicon area and increase potential die per wafer. Typically, wire bond pads are arranged in an in-line configuration where the pads are in a single row along the perimeter of the silicon chip. Alternatively, the bond pads can be placed in multiple rows in a staggered fashion around the silicon chip. In considering whether to utilize a staggered or an in-line bond pad layout, several tradeoffs should be considered between die size and the resulting bond pad size and corresponding assembly capabilities. The uniqueness of the staggered layout lies in the fact that a small effective pitch between wires can be achieved while maintaining a large bond pad. A larger bond pad also implies that less aggressive probe and assembly technology can he used. In the 35/70pm (i.e. 70pm pad pitch and 35pm effective pitch) staggered layout, a 25pm wire diameter coupled with a robust large tip capillary can be used to create a generous ball diameter of 55p. The main challenge in wire bonding a staggered design is the ability to create special wire looping to ensure no wire shortage between the rows. On the other hand, in the 47p in-line pad pitch layout, a 20pm wire diameter with a smaller tip capillary must be used to create a smaller ball diameter of 40p. As direct results of using a smaller wire diameter, the assembly development for 47pm in-lme design would need to consider the balance among the following criteria: (1) ball bond strength per area that meets industry-standard minimum value: (2) bonded ball diameter that results in ball bond placement accuracy Cpk of 1.33 or higher: and (3) wire loop height that helps reduce mold flow distubance to generate acceptable wire sweep at long wire length and tight pitch. This paper will begin with a brief comparison of the application space between in-line and staggered bond pad layouts with different U0 counts and core areas. The paper then discusses the assembly challenges associated with staggered design and in-line design. The focus in 35/70pm staggered wire bonding is the ability to consistently form a combination of low and high looping profiles for different rows of bond pads without causing wire shorting. Systematic experiments were conducted to evaluate wire bonder's stability in forming different wire loop heights and wire lengths for extended wire bondmg duration. Optimal wire loop height and pattem for staggered wire bondmg will be recommended. The discussion of 47pm in-line assembly development will focus on the wire bonding process. Wire bond parameter optimization and capillary design were critical to achieve both ball size reduction and bond strength stability. Wire loop height and scheme were also optimized to minimize wire sweep during encapsulation.

Driven for further silicon reduction, wireless applications utilize Copper interconnection and increase metal layer count from three to five layers. More aggressive ESD structures placed under the bond pads offer a significant opportunity for additional die area and cost reduction. Capping Copper bond pads with Aluminum was selected as the primacy approach for probing and wire bonding Copper devices. There exists an integral relationship between probe damage on the bond pads and the subsequent wire-bondability. As the pad geometry gets smaller, the ratio of the area of probe damage to the bond pad size will get proportionally larger, thereby reducing the available Aluminum necessary to form reliable Gold-Aluminum intermetallic coverage. This paper will describe probe and assembly processes developed for a fine pitch three-metal layer Copper interconnect device with ESD structures placed under bond pads. The relationship between probe conditions and wire-bondability were examined. Ball shear, wire rip and corresponding failure modes were evaluated at various readpoints of thermal aging studies to evaluate the integrity of ball bonds onto the metal stack. Reliability assessment was also performed. Based on the investigations studying the relationship among the pad structures, probe and wire bond quality, recommendations were derived to ensure high quality, stable and reliable bonds for fine pitch wire bonding on multi-layer Copper interconnect devices.

Driven for further silicon reduction, wireless applications utilize copper interconnection and increase metal layer count from three to five layers. More aggressive ESD structures placed under the bond pads offer a significant opportunity for additional die area and cost reduction. Capping copper bond pads with aluminum was selected as the primary approach for probing and wire bonding of copper devices. There is an integral relationship between probe damage on the bond pads and subsequent wire-bondability. As the pad geometry decreases, the ratio of the area of probe damage to the bond pad size becomes proportionally larger, thereby reducing the available aluminum necessary to form reliable gold-aluminum intermetallic coverage. This paper describes probe and assembly processes developed for a fine pitch three-metal layer copper interconnect device with ESD structures placed under the bond pads. The relationship between probe conditions and wire-bondability were examined. Ball shear, wire rip and corresponding failure modes were evaluated at various read points of thermal aging studies to evaluate the integrity of ball bonds to the metal stack. Reliability assessment was also performed. Based on the investigations studying the relationship between the pad structures, probe and wire bond quality, recommendations were derived to ensure high quality, stable and reliable bonds for fine pitch wire bonding on multi-layer copper interconnect devices