Scan chain (SC) is a widely used technique in recent VLSI chips to ease the test process of these chips. SCs enhance the observability and controllability of memory elements such as latches and flip-flops used in sequential parts of the chips. In this paper we propose a novel scan chain architecture which can effectively tolerate bit flip errors due to particle strikes. The proposed architecture is based on the use of redundant transistors in memory elements of the chip. Redundant transistors are added in a way which enables the memory elements to recover the stored value in the case of bit flip error occurrence in both test and normal modes of operation. Fault tolerance capability and energy consumption of the proposed scan architecture are compared with the previously proposed scan chains by the means of Spice simulations. Results of the simulation reveal that the proposed architecture has at least 40% improvement in reliability of test process while its power consumption overhead is at most 10% in both normal and test modes of operation.

This paper 3 addresses the accuracy of predictions in stock exchange using data mining methods. To do this we modeled the problem by means of a time series. After this, a novel data mining technique is used to classify data. The proposed technique combines the advantages of time series analysis and data mining approaches in order to enhance the prediction accuracy. In order to evaluate the proposed technique, it is compared with the well known data mining techniques. In comparisons we used the Dow Jones Industrial data for all methods to have fair comparison. Results show that the proposed technique has at least 34% improvement in prediction accuracy. Keywords-stock exchange; data mining; prediction;