Successful deployment of wireless sensor and actuator networks in sufficient numbers to provide true ambient intelligence requires the confluence of several disciplines including networking, low power RF and digital IC design, MEMS techniques, energy scavenging, and packaging. Progress in each of these areas has been documented and proof-of-concept prototypes have been tested. Research in RF transceiver design utilizing bulk acoustic wave resonators has yielded fully integrated, ultralow power transceivers. Novel digital circuit design techniques, including aggressive power management, robust subthreshold logic operation, and ultralow voltage SRAM with data retention enable efficient computation. These technological advances should be accompanied by novel opportunistic networking and media access techniques to provide robustness and decrease the duty cycle of the node. Future challenges include the integration of a sub-50 mu W carrier sense detector for asynchronous and non-beaconed receiver wake-up, efficient hybrid energy scavenging power generation, and cheap, robust three-dimensional packaging techniques.

Localization (or locationing) is a central concern for ubiquitous self-configuring sensor networks. The implementation of a distributed, least-squares-based localization algorithm is presented. Low power and energy dissipation are key requirements for sensor networks. As part of the sensor network, the localization system must also conform to these requirements. An ultra-low-power and dedicated hardware implementation of the localization system is therefore presented. The cost of fixed-point implementation is also investigated. The design is implemented in a 0.13 /spl mu/ CMOS process. It dissipates 1.7 mW of active power and 0.122 nJ/op of active energy with a silicon area of 0.55 mm/sup 2/. The mean calculated location error due to fixed-point implementation is shown to be 6%.

The Quark node combines off-the-shelf components and two custom CMOS chips to implement a PicoRadio wireless sensor-network node that runs solely from energy scavenged from the environment. The node supports a >10m indoor transmission range with automatic multi-hop routing for longer distances. Node functionality includes a 50kbps on-off keyed physical layer, a cycled-receiver MAC algorithm with dynamic ID assignment, a directed flooding network routing algorithm, and a Hop-TERRAIN location computation algorithm. The first custom die is a 0.13μm CMOS digital processor for the baseband, data-link, network, and application layers of the protocol stack. The second custom die is a 1.9GHz two-channel transceiver designed in 0.13μm CMOS for peer-to-peer communication. The 1.9GHz antenna is implemented as a board trace to reduce node cost. Keywords— Wireless sensor networks, Network connectivity chips, Low-power design, VLSI, Energy-scavenging, Networking Algorithms, Locationing

Synchronization is increasingly important in wireless communication devices. Synchronization performance is critical to system performance and, it is where a large amount of design time and receiver area and power is spent. Not only is synchronization important, but the relevance is increasing due to four factors: 1. Decreased transmit distances use lower transmit power and, therefore, receiver power begins to dominate. 2. The wireless channel is more frequency selective at higher transmission speeds which require increased synchronization functionality. 3. Trends toward higher bandwidth efficiency moves modulation to higher order constellations where synchronization specifications are tighter. 4. The push for integration moves RF functionality to digital CMOS processes with low supply voltages forcing the synchronization system to contend with more front-end nonidealities. There are few places where the whole topic of synchronization is covered and fewer still where the power consumption is considered. This research shows that significant system power savings can be realized through systematic exploration of synchronization power consumption. 2 This dissertation sets up a framework for the systematic exploration of power consumption in synchronization systems, applies this framework to a few representative problems, and uses some system examples to show the impact of this type of exploration. At the component level, frequency estimation and interpolation are investigated. It is shown that frequency estimation power reductions of up to 4x are possible while simultaneously decreasing convergence time by up to 4x. For interpolation, it is shown that proper parameter selection can result in a 10x reduction in power consumption. At the system level, two non standards-based communication systems are considered. PNII is a 1.6 Mbps personal area network system for wireless intercom type applications over short distances (10-30 m). The original system's frequency and phase estimation blocks are redesigned using the framework developed here. Simultaneous reductions of 66% in synchronization energy consumption and 72% in convergence time are achieved. PN3 is a 50 Kbps system designed for use in wireless sensor network applications. A 300uW synchronization system was designed for PN3. This is low enough so that further reduction has very little impact on system energy consumption. i Acknowledgements I would like to thank my advisor, Jan Rabaey, for his grand vision and subtle guidance (except when otherwise required). If I am half as successful in my career as he has been in his, I will be fulfilled. I would also like to thank him, in conjunction with Bob …