Using electrical public transportation systems is increasing dramatically. It is therefore highly significant to design these upcoming types of transport properly. The designing urban electric transportation system can be studied and modelled by mathematical equations. Besides, several methods have been proposed to plan these systems in recent years. Designing a travel profile is one of the most crucial parts of these methods. In this paper a travel profile for the fully electric buses named as Urbino-12 Electric, and three stations is designed and examined in Milan, Italy as a case study. Firstly, the used route data are obtained from the Google Maps’ tool. Next, the manufacturer’s catalogues and magazines are used to collect the vehicle data. Finally, computations were performed by Excel spreadsheets. The results show that the designed path in the proposed travel profile is covered at a commercial speed of 16.10 km/h, requiring 1.7 kWh of electrical energy that is regarded as frugal and profitable.

This paper presents a new mathematical approach to design an asynchronous pulse width modulation (APWM) for the switched mode power supply (SMPS). Unlike the conventional APWM that utilises a Hysteretic comparator based Asynchronous Pulse Width Modulation (HAPWM) to provide the self-oscillating property, the proposed APWM is based on a Binary comparator based Asynchronous Pulse Width Modulation (BAPWM) and a delay cell. This way, compared to the HAPWM, the mathematical analysis of the modulator is significantly simplified. This was achieved by replacing the describing function (DF) -based graphical method with a ?linearised mathematical model. The introduced mathematical approach is extended to study the behaviour of the higher order self-oscillating modulators in terms of the harmonic distortion. To confirm the effectiveness of the analytical derivations, the BAPWMs are employed in a classic DC-DC buck converter and the system-level simulation results are provided. It is concluded that there is an acceptable degree of similarity between the simulation results and the deployed analytical calculations for different orders of the modulators. Finally, to validate these analytical and simulation results and also to compare the BAPWM performance with its HAPWM counterpart, both modulators are implemented using off-the-shelf components and their measurement results are presented.

Falling and lack of control are some of the most essential problems of elderly people's lives. This phenomenon can be studied and modelled by mathematical equations. Besides, several models have been proposed to simulate the human body in recent years. The reverse pendulum is one of the most crucial procedures of these models. In this paper, human balance control system - similar to a two-legged robot- is examined. First, the mathematical equations of the human controller system are determined by the concept of a reverse pendulum model and indicate this is a parallel time delay system model. Then, the stability conditions of this model are expressed as a matrix linear inequality, with choosing the appropriate Lyapunov function. Finally, the performance and operation efficiency of the balancing system is determined by simulating a variety of time delays which creates the proper balance.

Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order charge pump Phase Locked Loop. In order to suppress spurs and reduce ripples on control voltage a third order loop filter is used. Power consumption is significantly reduced by simplifying the circuit structure of digital frequency divider. Advance process of silicon-Germanium BiCMOS (SiGe) is used to integrate high-performance Hetero-junction Bipolar Transistors (HBTs) and MOSFETs actives and passives. This technology has the advantage that its flicker noise (1/f) is very low.

Summary This paper presents an asynchronous pulse width modulation (APWM) approach for the analysis of a new class of the switched mode power supply (SMPS). The proposed APWM significantly simplified the mathematical analysis by utilizing a binary comparator (BAPWM) and a distinctive delay cell instead of hysteretic comparator. By this way, the mathematical analysis can be extended to study the behavior of high‐order self‐oscillating modulators in terms of key parameters such as the harmonic distortion and the stability. The performance of the proposed BAPWM is deeply analyzed for different orders of loop filters (here up to third order) in both time and frequency domain. To verify the effectiveness of the proposed analytical derivations, the BAPWMs are employed in a classic synchronous DC‐DC buck converter and its closed loop performance, in terms of stability, has been investigated. Then the converter is designed and simulated in 130‐nm CMOS technology to convert input voltage of 5 to 3.3 V with maximum load current of 1 A, using Spectre simulator. From the post‐layout simulation results, the peak efficiency conversion efficiency for 3.3 V output voltage is higher than 89%.

In this paper, a new methodology to improve the performance of continuous-time sigma-delta modulators is presented. The proposed structure notated as the time-based continuous-time sigma-delta modulator (TCSDM) utilizes the time encoding approach. Time-based encoding is known as a promising alternative to overcome the resolution problems of analog-to-digital converters (ADCs) in low-voltage circuits. The proposed TCSDM incorporates a novel time-based noise-shaped quantizer (NSQ) to significantly enhance its performance at a very low cost. Using the proposed NSQ, the modulator's noise-shaping order is improved by two without increasing the loop filter order. Furthermore, the implementation of the proposed TCSDM is alleviated using a new single-opamp resonator (SOR) to realize the loop filter. This significantly reduces the power consumption and saves more area. The concept is elaborated for a second-order TCSDM. The analytical calculations and the system-level simulation results are presented to verify the performance. To further confirm the effectiveness of the presented structure, the circuit-level implementation of the modulator is provided in TSMC 90nm CMOS technology. The results show that the proposed modulator achieves a dynamic range of 82dB over a 30MHz bandwidth while consuming less than 18.2mW power from a single 1V power supply. With the proposed NSQ and SOR, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced.

Summary Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.

Translation of the amplitude axis to the time axis can be a promising approach to alleviate the analog-to-digital converter’s resolution problems in low-voltage CMOS circuits. From this point of view, a noise-coupled time-based continuous-time sigma-delta modulator (TCSDM) based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented. Noise-coupling is realized by extracting the time quantization error of the TDC and injecting its delayed version to the input of the APWM. By using a novel implementation of the noise-coupling technique in the proposed TCSDM, the modulator’s noise-shaping order is improved by one. Unlike the conventional noise-coupled sigma-delta modulators, in the proposed structure, the need of an extra subtractor at the quantizer input is resolved through merging the excess loop delay compensation path with the proposed noise-coupling branch. Comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed time-based modulator. To confirm the validity of the proposed structure, the effects of main circuit non-idealities in the modulator’s performance are taken into consideration and the related simulation results are investigated. A digital-friendly implementation of the quantizer in the proposed modulator makes it suitable for low-voltage nanometer CMOS technologies.

Embedding time encoding into the quantizers, has been proven to be as a promising technique to overcome the data converter's resolution problems in low-voltage CMOS circuits. In this paper, an NTF-enhanced time-based continuous-time sigma delta modulator (TCSDM) with second-order noise-coupling is presented. The structure takes advantages from a combination of an asynchronous pulse width modulator (APWM) as a voltage to-time converter (VTC) and a time-to-digital converter (TDC) as a sampler to realize the time quantization. By using a novel implementation of the noise-coupling technique, the modulator's noise-shaping order is improved by two. The concept is elaborated for an NTF-enhanced second-order TCSDM and behavioral simulation results are presented to verify the performance. To further confirm the effectiveness of the structure, the circuit-level implementation of the modulator is provided in TSMC 90nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over a 30 MHz bandwidth while consuming less than 25 mW from a 1 V supply voltage. With the proposed time based noise-coupling structure, both the order and the bandwidth requirements of the loop filter can be relaxed, which in turn the analog complexity of the modulator is significantly reduced.

Translation of the amplitude axis to the time axis can be a promising alternative to overcome the resolution problems in analog-to-digital conversion in low-voltage CMOS circuits. From this point of view, design of a continuous-time sigma-delta modulator (CTSDM) with time domain quantization is presented. The proposed structure utilizes an asynchronous pulse width modulator (APWM) in order to map the data from the amplitude to the time. A classic flash time-to-digital converter (TDC) is also employed to digitize the PWM signal. The TDC is designed based on dual-edge triggered D-filp-flops (DE-DFF) to enhance the time resolution. A simple digital-to-time converter (DTC) is combined with the TDC to feed the single bit DAC with a serial data stream. The modulator leverages a third order active loop filter to exhibit a -60dB/dec noise shaping behavior. The systematic simulation results show SFDR and SNDR more than 82 dB and 75 dB for 40 MHz BW and time resolution of 80 psec, respectively. A digital-friendly implementation of the modulator makes it suitable for low-voltage nanometer CMOS technologies.

A high resolution highly linear low spur fractional time-to-digital converter (FTDC) for All Digital PLL (ADPLL) is presented. This FTDC employs a linear high gain time amplifier (TAMP) and a spur reduction digital filter to eliminate the spurs at the output. Unlike conventional TDCs, no delay line is utilized in the new FTDC, and hence no mismatch error cancelation technique is required. The FTDC structure is verified in theory and via simulation using an 180nm CMOS technology. The results illustrate a time resolution of 5 psec, differential nonlinearity (DNL) free dynamic range of about 350 psec, and the total power consumption, apart from the clock generator, of nearly 3mW.

Summary from only given. This paper presents a Fractional-N frequency synthesizer for WiMAX applications. Fractional-N phaselocked loop (PLL) architecture is selected for higher reference frequency, smaller division ratio, better frequency resolution, and the possibility of agile switching between the channels. Fractional-N synthesizer also alleviates PLL design constraints for phase noise and reference spur. Employing accumulator and linear feedback shift registers (LFSR) are the common techniques to provide the fractional division ratio. The generation of the fractional spurs is the main shortcoming due to utilizing these kinds of dithering circuits. A sigma-delta fractional-N frequency synthesizer (FS) improves the phase noise performance using a spur reduction method. Several kinds of sigma-delta structures are designed and verified via MATLAB/SIMULINK. Also the core of the synthesizer apart from the dithering circuits is simulated using ADS2009 in 0.13umCMOS technology. The simulation results illustrate a phase margin higher than 600, a phase noise lower than −120dBc/Hz and a settling time nearly to 4μsec. In order to reduce the power dissipation, TSPC logic is used to design a programmable frequency divider which consumes less than 1mW in 2GHz.

In this paper a PLL-based frequency synthesizer for WiMAX application is designed and simulated via MATLAB and ADS2008 using a 0.13umCMOS technology. Synthesizer with fractional-N structure is utilized to achieve high resolution, high switching speed, and high noise performance. To improve the linearity and the phase noise of the VCO, we employ a gain-linearizer block at the input of VCO. The simulation results show a phase margin higher than 50°, a phase noise lower than −120dBc/Hz @1MHz, and a settling time about 3µsec. In order to reduce the power dissipation, TSPC logic is used to design a programmable counter which needs less than 1mW in 2GHz.

This paper presents an integrated low-power, low-noise, continuous-time, active-filter for WiMAX applications. It is based on a noise shaping topology with using all core transistors in sub-threshold region. Using sub-threshold MOS transistors in the filter core gives possibility to stack up four transistors in low supply voltage. The proposed filter has significant reduction of in-band noise power with low power consumption. The designed low-pass (5MHz bandwidth) filter is simulated with Cadence in 0.18um 1P6M CMOS technology. It has out-of-band IIP3 above 13dBm with input referred noise of 14.3uV and the power dissipation of 1.25 mW.

The rapid scaling in modern CMOS technology has motivated the researchers to design new analog-to-digital converter (ADC) architectures that can properly work in lower supply voltage. An exchanging the data quantization procedure from the amplitude to the time domain, can be a promising alternative well adapt with the technology scaling. This paper is going to review the recent development in time-based noise-shaping ADCs, so-called as time-based sigma-delta modulators. Two of the most important architectures named as voltage-controlled oscillator (VCO) -based and time-to-digital (TDC) -based sigma-delta modulators (SDMs) are selected to be reviewed in this paper. The intrinsic advantages and limitations of the these structures are briefly explored. To confirm the effectiveness of the time-mode sigma-delta modulators, a TDC-based continuous-time sigma-delta modulator is proposed as an example and the related simulation results performed in MATLAB are illustrated. The simulation results show that the proposed modulator achieves a dynamic range of 67 dB over 30 MHz with the loop filter of order 2. The proposed TDC-based sigma-delta modulator shows the superiority of the time quantization approach in designing the wideband and less complex continuous-time SDMs.