We demonstrate open-eye 224G PAM4 transmission in a 1.6T-DR8 PIC implementing low-Vπ silicon-organic hybrid modulators (VπL < 0.5 V-mm) with >80 3 dB GHz bandwidth and a variant capable of 400G/λ (> 110 GHz) for 3.2T-DR8. Both PIC variants use commercial crosslinkable organic electro- optic materials.

We demonstrate an optical link at 53 Gbps using a 53G DSP with integrated electroabsorption modulator driver, a transmitter with heterogeneously integrated tunable lasers and electroabsorption modulators, and a receiver with monolithically integrated photodetectors and transimpedance amplifiers.

As deep neural networks (DNNs) revolutionize machine learning, energy consumption and throughput are emerging as fundamental limitations of CMOS electronics. This has motivated a search for new hardware architectures optimized for artificial intelligence, such as electronic systolic arrays, memristor crossbar arrays, and optical accelerators. Optical systems can perform linear matrix operations at exceptionally high rate and efficiency, motivating recent demonstrations of low latency linear algebra and optical energy consumption below a photon per multiply-accumulate operation. However, demonstrating systems that co-integrate both linear and nonlinear processing units in a single chip remains a central challenge. Here we introduce such a system in a scalable photonic integrated circuit (PIC), enabled by several key advances: (i) high-bandwidth and low-power programmable nonlinear optical function units (NOFUs); (ii) coherent matrix multiplication units (CMXUs); and (iii) in situ training with optical acceleration. We experimentally demonstrate this fully-integrated coherent optical neural network (FICONN) architecture for a 3-layer DNN comprising 12 NOFUs and three CMXUs operating in the telecom C-band. Using in situ training on a vowel classification task, the FICONN achieves 92.7% accuracy on a test set, which is identical to the accuracy obtained on a digital computer with the same number of weights. This work lends experimental evidence to theoretical proposals for in situ training, unlocking orders of magnitude improvements in the throughput of training data. Moreover, the FICONN opens the path to inference at nanosecond latency and femtojoule per operation energy efficiency.

This paper presents a digital control system for a fully integrated 16-channel optical transmitter, with the drivers, modulators, and control systems implemented on the same die in the Silicon Photonic-CMOS 45 nm GF Fotonix™ platform as part of a 1.8 Tbps optical link.

With the emergence of several open-market silicon photonics foundries, it is now possible to create a rich design IP ecosystem for co-designed electronics and photonics much like what exists for CMOS. Design reuse will accelerate time-to-market and enable significantly enhanced photonic system complexity.

We report an end-to-end photonic deep neural network processor, fabricated in a commercial CMOS process, that integrates optical matrix algebra and nonlinear function units onto a single chip and implements all-optical DNN inference and training.

We demonstrate a transmitter and receiver in a silicon photonics platform for O-band optical communication that monolithically incorporates a modulator driver, traveling-wave Mach-Zehnder modulator, control circuitry, photodetector, and TIA in the GlobalFoundries Fotonix™ (45SPCLO) platform. The transmitter and receiver show an open 112 Gbps PAM4 eye at a 4.3 pJ/bit energy efficiency, not including the laser. Extensive use of gain-peaking enables our modulator driver and TIA to achieve the high bandwidths needed in the 45 nm CMOS-silicon photonics process. Our results suggest an alternative to the frequent approach of bump-bonding BiCMOS drivers and TIAs to silicon photonics.

Advanced machine learning models are currently impossible to run on edge devices such as smart sensors and unmanned aerial vehicles owing to constraints on power, processing, and memory. We introduce an approach to machine learning inference based on delocalized analog processing across networks. In this approach, named Netcast, cloud-based "smart transceivers" stream weight data to edge devices, enabling ultraefficient photonic inference. We demonstrate image recognition at ultralow optical energy of 40 attojoules per multiply (<1 photon per multiply) at 98.8% (93%) classification accuracy. We reproduce this performance in a Boston-area field trial over 86 kilometers of deployed optical fiber, wavelength multiplexed over 3 terahertz of optical bandwidth. Netcast allows milliwatt-class edge devices with minimal memory and processing to compute at teraFLOPS rates reserved for high-power (>100 watts) cloud computers.

Alexander Sludds, Saumil Bandyopadhyay, Zaijun Chen, Zhizhen Zhong, Liane Bernstein, Darius Bunandar, Matthew Streshinsky, Ari Novack, Tom Baehr-Jones, Michael Hochberg, Manya Ghobadi, Ryan Hamerly, and Dirk Englund Research Laboratory of Electronics, MIT, Cambridge, MA, 02139, USA Computer Science and Artificial Intelligence Laboratory, MIT, Cambridge, MA, 02139, USA Nokia Corporation, 171 Madison Avenue Ste 1100, New York, NY, 10016, USA Luminous Computing Inc., 278 Castro St, Mountain View, CA, 94041 and NTT Research Inc., PHI Laboratories, 940 Stewart Drive, Sunnyvale, CA 94085, USA

We demonstrate the first multi-stage 8 × 8 silicon photonic switch with switching elements based on dual add-drop microrings with a compact footprint of 4 mm2. This device leverages co-design of the switch architecture and the switching elements with a well-balanced set of performance metrics. The switching elements are designed to have a 3-dB optical passband of 165 GHz, exhibiting off- and on-resonance losses of 0.67 dB and 2 dB, respectively. Full characterization of all switch paths shows an end-to-end on-chip loss between 4.4 and 9.6 dB, with worst-case crosstalk leakage averaged at −16 dB. Owing to the efficient doped waveguide thermo-optic phase shifters, the device features a tuning efficiency of 48.85 GHz/mW. The reconfiguration time of the switch fabric is measured to be 1.2 μs and 0.5 μs at the rise and fall edge, respectively. The dual-microring switching element together with the multi-stage architecture preserves an end-to-end passband over 55 GHz. We validate the switch performance with optical paths of varying numbers of on- and off-resonance switching elements – less than 2 dB power penalties are obtained for all data routings at 32 Gbps.

We demonstrate a real-time silicon-photonics-based 400GBASE-DR4 transceiver packaged in a QSFP-DD form factor. The performance of the transmitter including TDECQ, extinction ratio and OMA and receiver sensitivity are measured, all satisfying IEEE 400GBASE-DR4 specifications.

First demonstration of a dual-microring 8 x 8 silicon-photonic switch in a compact 4 mm(2) footprint shows 4.4-8.4 dB end-to-end on-chip loss, -16.75 dB first-order switching crosstalk, and 40 GHz switching bandwidth capable of high-data-rate datacenter transmissions.

Silicon Photonics (SiPh) is expected to be the technology platform to address next-generation optical interconnect solutions. By leveraging existing semiconductor production infrastructure and processes as well as building complex optical system-on-chip solutions by shrinking photonics and co-designing with electronics, SiPh enables opportunities for a wide range of fundamentally new applications.

Traditionally, the high-performance optical coherent communication TX has been a discrete assembly based on LiNbO3 modulators and III-V drivers. While delivering high bandwidth (BW) and linearity, such a platform is bulky and does not work for high-volume or intra-datacenter applications. Silicon photonics (SiPh) offers a Si-based platform for next-generation transceivers by integrating all required optical functions. But even in existing SiPH-based commercial modules, the driver generally remains a III-V-based chipset, impeding the path to an all-silicon solution. The challenge for an all-silicon-based coherent optical TX is in the simultaneous requirement of high differential voltage swing (Vppd), linearity and BW. In this work, we present a 130nmSiGe driver achieving a 6Vppd swing, 3.6% THD and small-signal BW over 40GHz. Co-packaged with a SiPh transceiver, the driver enables the same level of performance as LiNbO3 modulators with III-V drivers and demonstrates 272Gb/s dual-polarization (DP)-160AM transmission. This is enabled using (1) circuit techniques that achieve a BW extension ratio (BWER) of $4.5\times $ for the Mach-Zehnder modulator (MZM) driver while simultaneously achieving large swing ($\mathrm {V}_{\mathrm {p}\mathrm {p}\mathrm {d}}$=6V), high linearity (THD $=3.6$%) and mitigating breakdown voltage (BV) and reliability concerns with large Vppd; (2) pre-emphasis control in the driver output stage and gain control in the pre-driver VGA to compensate for the electro-optic (E/0) BW of the TX over corners; and (3) a monolithic integration of MZMs with a polarization rotator (PR) optimized for high-BW, low-crosstalk and co-integration with drivers for DP-OAM and DP-OPSK operation.

We present a co-designed silicon traveling wave modulator with a SiGe driver with 6Vpp effective swing. 34GBaud DP-16QAM is demonstrated with comparable ROSNR performance to a commercial CFP2-ACO.

We demonstrate an all-silicon-photonic coherent link, including a hybrid tunable laser with <100kHz linewidth, >45dB SMSR, and <-135dB/Hz RIN as light source for a BGA-packaged 64Gbaud coherent transceiver with direct edge-coupling to 10 mu m-MFD fiber. (C) 2018 The Authors(s)

We present a highly efficient polarization splitter and rotator (PSR), fabricated using 248 nm deep ultraviolet lithography on a silicon-on-insulator substrate. The PSR is based on a double-etched directional coupler with a length of 27 µm. The fabricated PSR yields a TM-to-TE conversion loss better than 0.5 dB and TE insertion loss better than 0.3 dB, with an ultra-low crosstalk (-20 dB) in the wavelength regime 1540-1570 nm.

We demonstrate a highly efficient grating coupler with center wavelength near 1310 nm fabricated on a silicon-on-insulator (SoI) wafer by 248-nm deep ultraviolet lithography. One of the lowest reported losses of 2 dB is achieved using feature sizes of 200 nm and without other process enhancements, such as polysilicon. The higher efficiency is obtained through improved mode-matching based on a novel genetic algorithm, which utilizes two different etch depths. The 3-dB bandwidth is 50 nm, and the back-reflection to the waveguide is better than 20 dB. The result shows low-loss coupling between waveguides and single-mode fibers for 1310~nm applications suitable for mass production on the commonly used 220-nm SoI platform.

We report a silicon nanophotonic parallel single mode transmitter and receiver with an aggregate data rate of 2.4 Tb/s. The transceiver is composed of 48 channels, each operating at 50 Gb/s. Bit error rate versus power measurements demonstrate that each transmitter channel is capable of operating at a BER of 10-9. The receiver is shown to provide open eyes at 50 Gb/s. Furthermore, insertion loss and sensitivity data of the transmitter show uniformity within 3 dB across all 48 channels.

We present the design and fabrication of complimentary metal-semiconductor field-effect transistors (MESFETs) monolithically integrated on a high-speed silicon photonics platform. The transistors were built in an existing silicon photonics process without any additional process steps or modifications to maintain consistent photonics performance. The MESFETs showed a threshold voltage of -1.4 and 2.0 V for NMES and PMES, respectively. The NMES transconductance was measured to be 46.4 μS/μm, and the cutoff frequency was shown to be 2.2 GHz. Transistors of this design can be simply integrated into silicon photonics platforms for on-chip feedback circuits.