Solid-state klystron modulators are typically based on oil-immersed high-voltage (HV) pulse transformers due to their high performance, robustness, and topological simplicity. However, in considering high-power multi-millisecond pulsed applications based on this topology, modulator power components and their design become increasingly complicated and, correspondingly, modulator size becomes problematic. In this article, practical models for the characterization and design of each main power component forming the pulse transformer-based modulator topology are developed. These models are then integrated in forming a complete optimization procedure suitable for long-pulse high-power applications. The developed design procedure is used in considering a complete pulse transformer-based modulator design for the case of the European Spallation Source klystron modulator requirements (a pulse amplitude of 115 kV/100 A, a pulselength of 3.5 ms, and a pulse repetition rate 14 Hz). The performance of the individual components as well as the complete modulator is studied and validated through the circuit simulation. Finally, fixing the pulse power parameters to that of typical high-power klystron load requirements, the optimization procedure is used in a parametric study sweeping the application pulselength and pulse repetition rate to explore the possibilities and limitations of the pulse transformer-based modulator topology.

It has been proposed that the relatively low duty cycle of the European Spallation Source (ESS) linac allows acceleration of additional $\mathbf{H}^{-}$ ion pulses interleaved with the baseline proton pulses, representing a unique opportunity to construct a neutrino super beam (ESSnuSB) facility of unparalleled luminosity. Coupled with a distant Cherenkov detector, it is believed that evidence of CP violations in leptons could be obtained, representing a significant step towards understanding the matter/antimatter asymmetry. In this paper, several such interleaved pulsing schemes are considered from the perspective of the klystron modulators and the RF power system in investigating the possibility to realize the ESSnuSB. Conserving the required output RF energy, these pulsing schemes vary in terms of 1) number of added H- ion pulses per baseline cycle, 2) pulse amplitude and 3) pulse length. Each prospective pulsing scheme offers unique advantages while differently impacting klystron modulator performance. Whereas the ESS linac baseline design requires 33 klystron modulators (rated for pulse amplitude 115kV/4x25A, pulse length 3.5ms and pulse repetition rate 14Hz; each modulator powering 4 parallel klystrons rated 1.6MWpk at 704MHz), the proposed upgrade requires doubling the baseline linac average output power and thus either doubling the capacity of existing modulators or the procurement of additional modulator systems. In order to evaluate and compare the merit of these solutions from a system perspective, a mathematical framework connecting the attributes of the proposed pulsing schemes to the power transfer curves of the klystrons and subsequently to the performance of the klystron modulators is developed. Finally, a preferred solution is selected and the impact on grid-to-RF efficiency, modulator average input power quality, total upgrade cost and required additional system size is assessed.

Modern high-voltage high-power pulsed modulators typically generate pulses by discharging energy stored in one or more capacitor banks into the load. The capacitor discharge manifests itself as output pulse droop which must be compensated for. To eliminate such droop, modulators utilizing pulse transformers require external circuitry and, typically, passive resonant bouncer circuits are used. For long-pulse applications, however, electronic bouncer circuits operated in closed loop are preferred due to their compactness, efficiency, precision, and resilience to aging effects. Electronic bouncers may also be used in applications with varying pulselength and/or pulse repetition rate. In this article, design models are developed for both the modulator capacitor bank as well as each electronic bouncer circuit component. The design models are integrated in a global optimization routine used to study design tradeoffs between the modulator capacitor bank and the electronic bouncer, as well as between system efficiency and system volume. An optimization case study based on European Spallation Source modulator requirements (pulse amplitude 115 kV/100 A, pulselength 3.5 ms, pulse repetition rate 14 Hz, combined pulse flat top ripple and droop <; 0.15%) is provided, and an optimal design solution is selected and validated through characterization in both circuit simulation and 3-D finite element analysis. Finally, the performance of the chosen electronic bouncer solution is compared to that of an optimized design based on the conventional passive resonant bouncer circuit.

Solid-state klystron modulators are typically based on oil-immersed high-voltage (HV) pulse transformers because of their high performance, robustness, simplicity, and straightforward design. However, pulse transformer size is fundamentally linked to application pulse length, pulse power, and pulse rise time. For high-power applications transformer size quickly becomes very problematic when approaching pulse lengths on the order of one millisecond. This article presents a systematic study of the applicability of HV pulse transformers for such long-pulse high-power applications. Both the single-layer and pancake winding techniques are evaluated, keeping reduction of transformer volume as the main design objective. First, design models and efficient optimization procedures are developed. The proposed models are validated through circuit simulation, 3-D finite element analysis, and comparison with a commercial HV long-pulse transformer. Then, the developed optimization procedure is used in studying the evolution of pulse transformer size when pulse length is varied from 500 μs to 5 ms assuming peak pulse power requirements corresponding to that of the European Spallation Source (ESS) klystron modulators (115 kV, 100 A, 14 Hz). Finally, the developed trends are used to derive general analytical equations expressing maximum attainable pulse length as a function of application parameters and system constraints.

The stacked multilevel (SML) klystron modulator topology has been suggested as an alternative to conventional pulse transformer-based topologies in an attempt to improve output pulse performance and reduce system size for long-pulse applications. In this topology, a power converter chain including a high-frequency transformer generates the output pulse in a pulse modulation/demodulation scheme, eliminating the direct size-pulse length dependency inherently associated with pulse transformers while allowing a higher degree of freedom in design. This article details the design of the SML pulse generation stage with particular focus on the aspects of system extents volume, system efficiency, converter lifetime, and complexity. Key component design equations are derived and integrated into an optimal design routine used to primarily study trade-offs between volume and efficiency, as well as in selecting a design for ESS klystron modulator requirements—pulse amplitude 115 kV/100 A, pulse length 3.5 ms, pulse repetition rate 14 Hz, efficiency > 90%, and lifetime > 25 years. The chosen design is characterized through circuit simulation and 3-D finite element analysis, and is validated in power testing.

The stacked multi-level (SML) klystron modulator topology has been suggested as an alternative to conventional pulse transformer based topologies in an attempt to improve output pulse performance and reduce system size for long pulse applications. In this topology, a power converter chain including a high frequency transformer generates the output pulse in a pulse modulation/demodulation scheme, eliminating the direct size-pulse length dependency while allowing higher degree of freedom in design. However, increased complexity necessitates careful consideration from a system perspective to ensure appropriate component selection and design. First, from the perspective of the semiconductor switches, the pulsed nature of the load must be taken into account. High modulator average and peak powers are combined into a power cycling problem where lifetime issues must be managed when selecting semiconductor technology and converter operating frequency. Simultaneously, these considerations are directly coupled to the design of the high voltage high frequency transformer, the largest component in the SML chain, key in reducing modulator footprint and volume. In addition, appropriate passive components (snubbers) must be chosen with respect to transformer leakage inductance, switching frequency and switch ratings to constrain voltage overshoot without deteriorating system efficiency. In this paper, these integrated design considerations are combined with a catalog of IGBT switches available on the market to form an optimization algorithm set to minimize transformer volume, indicative of system oil tank volume, while ensuring high system efficiency and long semiconductor lifetime. The tradeoffs between system efficiency and volume are studied. Finally, the algorithm is used to outline the design procedure for a system rated for pulse amplitude 115 kV / 100 A, pulse length 3.5 ms, pulse repetition rate 14 Hz, efficiency>91%, lifetime>25 years. The derived design is validated through circuit simulation, 3D finite element analysis, and experiments.

In order to generate high-voltage high-pulsed power, klystron modulators necessarily contain at least one capacitor bank charging structure supplying the energy to be released during the pulse. Conventional charging structures are based on ac/dc front-end units typically based on diode rectifiers combined with power charging structures operated in on/off mode as a second stage, producing prohibitive levels of grid flicker and harmonic contents on the ac grid side while operating at suboptimal power factor. These problems are usually corrected by both costly and spacious external grid compensators. Today, the increased demand on both accelerator peak power and pulselength (translating into higher average power), in conjunction with stricter regulations and standards represent additional challenges also in modulator design. An alternative method for capacitor bank charging, in a steady state allowing for the complete reduction of grid flicker as well as ac line current harmonics and reactive power, was presented by the authors in a preceding publication. This paper presents in further detail the benefits of the proposed power electronic structure and associated control scheme in the context of a review of other solutions suggested for constant power charging and flicker mitigation. This paper also contains a complete description of the proposed control scheme as well as further experimental results, including a thorough assessment of its performance under transient conditions. All experimental results were obtained on a klystron modulator prototype rated for long pulses (3.5 ms), high voltage (115 kV), and high pulsed power (peak power > 2 MW).

Solid state klystron modulators are typically based on oil-immersed pulse transformers due to their high performance, robustness, simplicity and straightforward design. However, the size of such transformers are highly impacted by pulse power, output voltage, pulse length, and required rise time; key parameters which are difficult to combine in long pulse high power linac applications. In this paper, pulse transformer design models for two winding configurations (single layer winding and pancake winding), including calculation of parasitic elements, are developed and validated in a 3D finite element analysis environment. These models are then employed in a global optimal design procedure used to study the evolution of pulse transformer volume as pulse length is increased from 500 mu s to 4 ms while constraining maximum pulse rise time and overshoot. The impact of required pulse power, pulse rise time, and system size is also studied. The single layer winding based on standard enameled round wire is first investigated under size constraints representing a limit imposed by manufacturability and maintainability, validating the optimization procedure and demonstrating that, for this winding technique, sub-optimal rise time and therefore transformer size is attained for long pulse high power applications. Consequently, the pancake winding configuration is evaluated under the same conditions, demonstrating that, although more complex and costly, its flexibility allows a more compact design. Finally, a pulse transformer rated for pulse amplitude 115 kV, output current 25 A, pulse length 2.8 ms, and 0-99% rise time <300 mu s is designed, demonstrating the design procedure and showcasing limitations experienced in design. Its performance is assessed in circuit simulation whereas the validity of the derived parameters is demonstrated through finite element analysis.

In order to generate high voltage high pulsed power, klystron modulators necessarily contain at least one capacitor bank charging structure supplying the energy to be released during the pulse. Conventional charging structures are based on AC/DC front-end units typically based on diode rectifiers combined with on/off controlled power charging structures as a second stage, producing prohibitive levels of grid flicker and harmonic contents on the AC grid side while operating at suboptimal power factor; problems usually corrected by both costly and spacious external grid compensators. Today, the increased demand on both accelerator peak power and pulse length (translating into higher average power), in conjunction with stricter regulations and standards represent additional challenges also in modulators' design. An alternative method for capacitor bank charging, implying use of a combination of a grid connected Active Front End (AFE) and a DC/DC buck converter is proposed. The AFE controls the AC line current to be sinusoidal (reducing harmonic content) and in phase with the AC line voltage (minimizing reactive power). The DC/DC converter is regulated in current mode for instantaneous constant power charging by measuring capacitor bank voltage and adjusting the current reference to match the exact average power consumed by the load over a pulse repetition cycle, allowing in steady state for complete reduction of the grid flicker despite the heavily pulsed loads. This paper explains in detail the working principle behind the proposed power electronic structure and associated control methodology, and provides successful power quality results obtained both in simulation and from experiments carried out on a klystron modulator prototype delivering long pulses (3.5 ms), high voltage (115 kV), and high pulsed power (peak power > 2 MW).

The ESS Linac project, phase I, requires 12 long pulse klystron modulators with compact footprint, high pulse power and improved quality both on the output pulse waveform and on the input AC power line. Conventional long pulse modulators are typically based on HV pulse transformers and commonly exhibit poor efficiency, low power density, large footprint and cost, with still limited performance on pulse rise time, pulse flat-top accuracy and AC power line quality (flicker, current harmonic distortion, power factor). This paper presents the Stacked Multi-Level (SML) klystron modulator topology, a novel modular concept based on the association of several HV modules in series at their output, each formed by a high voltage and high-frequency transformer, a HV diode rectifier bridge and a low pass filter. Each HV module is fed from a low voltage power electronic inverter at ground potential since the transformer provides the required galvanic isolation between primary and secondary windings. This topology is believed to better suit the application and better satisfy ESS requirements, directly addressing the mentioned shortcomings of conventional topologies. The development and validation of this new concept has included the design and construction of a reduced scale prototype with the potential of delivering long (3.5 ms) and high quality pulses (0-99% rise time < 120 mu s and flat top ripple < 0.15%) with pulse amplitudes up to 115 kV and pulse power up to 2 MW, while maintaining excellent AC grid power quality (low flicker operation < 0.2%, sinusoidal current absorption with total harmonic distortion < 3%, and unitary power factor). The paper describes the main features of the topology and the main design aspects, presenting results both from simulation models, including parasitic elements, and from an experimental setup.

High voltage long pulse klystron modulators typically use pulse transformers, where the length of the pulse dictates the size of the transformer. Recent advancements in power electronics applied to modulator technology, in order to facilitate multi-millisecond long pulse generation, instead suggests use of high frequency transformers in a high frequency pulse modulation/demodulation scheme, eliminating the size-pulse length dependency. The Stacked Multi-Level (SML) topology is built around this technique, where a cascaded power converters chain inverts, amplifies, rectifies and filters the voltage following a capacitor bank charging stage in order to generate high voltage pulses. In a modulator built to European Spallation Source requirements, six such stages are connected in series at respective output, reducing stress on each module and increasing output ripple frequency, limiting the need of filtering, i.e. further reducing size, pulse rise time and stored energy. While use of this topology has demonstrated reduction in modulator footprint and cost for typical long pulse applications, use of high frequency switching obliges strict transformer core flux control in order to avoid transformer saturation due to undesired DC voltage components generated by the inverter without resorting to transformer oversizing. Several methods implementing similar modes of control already exist, but commonly require additional sensors which may not be available or practical for inclusion in high voltage environments. Furthermore, available methods assume constant operation whereas the pulseforming stage needs to systematically switch off completely between pulses, creating an additional problem related to remanent core flux and saturation; it must be ensured that the core flux is properly set before the following pulse is to be generated, or pulse-to-pulse flux accumulation may entail transformer saturation. This paper describes the above problems in detail and outlines a practical algorithm, assessing its capability to control flux independent of pulse duration while minimizing rise time increase.

The European Spallation Source (Lund, Sweden) is an under construction multi-disciplinary research facility to be based around a Linear Particle Accelerator which is to provide 2.86 ms long proton pulses at 2 GeV at a pulse repetition rate of 14 Hz, representing an average beam power of 5 MW. To accommodate the requirements of the proton linac, a large number of klystrons driven by power electronic modulators will be needed. Conventional long pulse modulators are pulse transformer based and commonly exhibit poor efficiency, low power density, large footprint and cost. In addition, these topologies due to their nature in combination with the above cited high peak power requirement for short periods of time commonly produce prohibitive levels of flicker and harmonic content while operating at suboptimal power factor, problems usually corrected by both costly and spacious external grid compensators. This paper presents the stacked multi-level (SML) klystron modulator topology, a novel, modular concept based on high-frequency transformers and rectifier bridges stacked in series, believed to better suit the application and better satisfy ESS requirements, directly addressing the mentioned shortcomings of conventional topologies. The development of this new klystron modulator topology has included the design and construction of a reduced scale prototype with the potential of delivering long (3.5 ms) high quality dc pulses (0-99% rise time of less than 100 μs and flat top ripple less than that of 0.15%) of high voltage (115 kV) and high power (peak power > 2 MW) while on its own maintaining excellent AC grid power quality (low flicker operation <; 0.2%, sinusoidal current absorption with total harmonic distortion <; 3%, and unitary power factor). The paper in detail describes the essential features of the topology and outlines the working principle, presenting results from both simulation and experimental work.

A novel Stacked Multi-Level (SML) modulator topology optimized for long pulse and high average power applications has been developed at ESS. It utilizes six identical modules connected in series at the HV output side and fed in parallel from the low voltage side. Each one is formed by one HF inverter, one step-up transformer, one HV rectifier bridge and one HV passive filter. They are supplied, in groups of two, from three capacitor banks which in turn will be charged from the low voltage electrical grid by using three groups of active AC/DC and DC/DC converters. Industrial standard power electronic components are used at the primary stage, which are placed in conventional electrical cabinets. Only few special components (transformers, rectifiers, filters) are required to be placed in an oil tank. A technology demonstrator rated for 115kV/20A and 3.5ms/14Hz is at the final phase of construction. The main power conversion circuit and regulation principles will be described and details on the design and construction of the main subsystems will be given. Simulation and experimental results will be given showing the achieved performance in terms of HV pulse quality and AC grid power quality. (Less)

ESS, the European Spallation Source, will be a major user facility at which researchers from academia and industry will investigate scientific questions using neutron beams. ESS will deliver its protons to a solid, rotating tungsten target, which will in turn generate neutrons. A linear accelerator (Linac) creates protons at the ion source, accelerates them to an appropriate energy and steers them onto the target to create neutrons via the spallation process. Among the cryogenic accelerating sections, there are "warm" magnets for correcting the proton beam "optics". This paper reports the chosen strategies for the power converters in these LWUs (Linac Warm Units). Amongst the power converters, we will highlight the 4-quadrant corrector magnets ones, based on a high precision and high bandwidth MOSFET H-bridge chopper, and a proposed novel topology for pulsed quadrupole magnets, instead of traditional DC ones. We will also demonstrate the interest of using pulsed magnets in place of DC ones in low duty-cycle Linacs, reducing the magnet losses and therefore the power consumption up-to 90%.