This paper describes a high-speed D/A converter design for mixed-mode systems. Capacitive coupling induced by inter-chip interconnects should be considered for mixed-mode systems, and on-chip interconnects should be treated as transmission lines in the circuit simulation as operating speed reaches the GHz range. A robust FIFO built in the D/A converter can absorb data-dependent input timing variance, the worst-case margin of which is /spl plusmn/1.5/spl times/T/sub CLK/. Distributed LCR transmission line models for on-chip interconnects produce more accurate simulation results at 1 GHz clock frequency than lumped models. Measurement results verify the accuracy of the interconnect models. Behavioral modeling methodology is also presented in this paper for optimized D/A converter design.

This paper presents a 1-GS/s, 12-bit SiGe BiCMOS D/A converter combined with high-speed low-spurious BiCMOS current switches and an efficient calibration method for current mismatch. Experimental results show a reduction in INL and DNL errors from +35.5/-62.2 LSB to +4.1/-3.4 LSB and from +8.1/-10.3 LSB to +6.2/-1.2 LSB, respectively, after calibration. SFDR performance is 72.3 dBc at output frequency of 1.82 MHz and 50.0 dBc at output frequency of 334.39 MHz, when the sampling clock frequency is 1 GHz. Power consumption is about 950 mW at 100.48MHz output frequency and -3.3 V power supply.