In the next decade, it is expected that integrated circuits having 5–7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 m/cm2 level. Multilevel interconnect technology needs are presently generating processing and structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials and electrical requirements which must be addressed by the interconnect engineer. A comparison of interconnect systems based on different conductor materials will be presented.

Discusses the use of special test structures and algorithms needed to extract the defect characteristics for accurate yield estimation. By using the double bridge test structure, which can be applied to obtain defect size distributions in the metal layer, the basic elements of the defect extraction algorithms are demonstrated. Data from a fabrication experiment is used to illustrate the algorithms