The IBM z14 platform brings together numerous innovations that collectively provide considerable performance gains over prior designs for the full spectrum of modern workloads being run on today's enterprise systems. These workloads range from traditional online transaction processing and batch workloads to Linux-based and cloud-based workloads, leveraging advances in analytics, mobile transaction processing, social data mining, cognitive applications, security (blockchain), and other areas. The performance gains in the z14 platform required advancements in the processor hardware microarchitecture, physical design, and instruction-set architecture, as well as in the firmware and hypervisor stacks. The result is a comprehensive platform solution that enables efficient multiprocessor scaling for large single-image partitions and mixed-workload multipartition environments within a single platform, while remaining responsive to the "bursty " demands of batch and transaction-based workloads. The performance gains present in the z14 are a direct result of the collaborative efforts between diverse teams within IBM working together to produce advancements in hardware, firmware, and software that outpace the gains of the individual contributions. In this paper, we discuss these results with a focus on the client value delivered through system performance and workload responsiveness.

The IBM zEnterprise® 196 (z196) system, announced in the second quarter of 2010, is the latest generation of the IBM System z® mainframe. The system is designed with a new microprocessor and memory subsystems, which distinguishes it from its z10® predecessor. The system has up to 40% improvement in performance for traditional z/OS® workloads and carries up to 60% more capacity when compared with its z10 predecessor. The memory subsystem has four levels of cache hierarchy (L1 through L4) and constructs the L3 and L4 caches with embedded DRAM silicon technology, which achieves approximately three times the cache density over traditional static RAM technology. The microprocessor has 50% more decode and dispatch bandwidth when compared with the z10 microprocessor, as well as an out-of-order design that can issue and execute up to five instructions every single cycle. The microprocessor has an advanced branch prediction structure and employs enhanced store queue management algorithms. At the date of product announcement, the microprocessor was the fastest complex-instruction-set computing processor in the industry, running at a sustained 5.2 GHz, executing approximately 1,100 instructions, 220 of which are cracked into reduced-instruction-set computing-type operations, to achieve large performance gains in legacy online transaction processing and compute-intensive workloads.