Self-reconfiguration and adaptivity are important new concepts For reconfigurable hardware. The benefits include, for example, a reduction in power dissipation by sharing resources therefore requiring smaller reconfigurable chips. Idle applications are substituted on demand by actually needed functions. As a result, the number of possible functions controlled by Such systems increases without raising, the number of additionally required processing elements. Parallel tasks (functions) in hardware execute more efficiently compared with sequential microprocessors. The high performance of reconfigurable hardware and the possibility of hardware parallelization, help to overcome increasing problems of data processing, with traditional microcontroller and microprocessors in future complex electronic systems. A relevant issue is the use of adaptive reconfigurable systems in real-time applications, which is one of the basic conditions for a variety of target applications. New approaches to create systems, which are able to manage their own configuration are called run-time systems. These systems use the flexibility of e.g. an FPGA by partially changing the configuration. Only the necessary functions are configured in the chip's memory. On demand one or more functions can be substituted by another while other parts stay operative. The ALadyn project targets exactly this kind of adaptive system approach and investigates in the physical hardware realization, system modeling and development tools.

The paper describes a new approach of a flexible run-time system for handling dynamic function reconfiguration in fine-grain Virtex FPGAs, whereas the fulfillment of given real-time constraints are central. Moreover, the detailed evaluation and measurement of the power consumption situation during this dynamic reconfiguration process is essential for realistically quantifying the power loss of fine-grain FPGAs during dynamic reconfiguration processes. This kind of real-time run-time systems and power analysis give the designer and user the possibility to compare FPGA implementation alternatives and to apply the required functionality reconfigurations during the selected application scenarios. Thus, a qualified decision can be done between finegrain FPGAs of different sizes and different dynamic reconfiguration frequencies, e.g. using smaller and more cost- as well as power-efficient FPGAs by temporarily outsourcing suitable functionalities.

Reconfigurable computing systems have already shown their abilities to accelerate embedded hardware/software systems. Since standard processor-based embedded applications have come to their limits we need new concepts for controlling and managing embedded, possibly distributed, reconfigurable hardware/software computing systems. Succeeding to previous papers which dealt with management aspects of run-time reconfigurable systems and related AI-approaches this contribution describes an approach and proof of concept of a transparent communication mechanism between the application layer and its possibly distributed and reconfigurable hardware/software sub-function modules.

Xilinx Virtex FPGAs have the possibility of dynamical partial runtime reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution of parts in reconfiguration memory, the amount of neccesary memory increases. The sum of memory amounts which have to be provided for the configuration data is not negligible. This fact suggests the investigation of compressing data before they are stored in memory modules of a system. The compressed bitstream data has to be decrompressed before transferring it to the FPGA. This paper shows an approach to compressing configuration data at design time and decompressing them with a hardware module implemented on FPGA while on runtime.

This contribution presents a new approach for allocating suitable function-implementation variants depending on given quality-of-service function-requirements for run-time reconfigurable multi-device systems. Our approach adapts methodologies from the domain of knowledge-based systems which can be used for doing run-time hardware/software resource usage optimizations.

As the number of built in microcontroller-; and ASIC-based automotive control devices grows, it will become an increasing problem for the most automobile manufacturers since communication, power consumption, available space and cost become important issues for a growing number of engine control units needed for future automotive applications. This contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function-multiplex which can be a possible solution for the arising problems as mentioned above.

Zusammenfassung Der Beitrag motiviert und beschreibt den Aufbau sowie Einsatz dynamisch rekonfigurierbarer Hardwarearchitekturen in intelligenten, laufzeitadaptiven Systemen und vergleicht diese Technologien mit den relevanten organischen Aspekten der genetischen Kontrolle der Entwicklung und Funktion biologischer Zellen.

We present a new approach for a function allocation manager supporting multiple reconfigurable devices. It is a rule-based approach considering resource usage and power consumption. An essential main component which is in the focus of this contribution is a retrieval-unit for function-requests. This unit adopts methodologies from the domain of knowledge-based systems by accounting quality-of-service related parameters from the calling application's function request.

Summary form only given. The handling of an increasing number of automotive comfort functionalities has become a significant problem for the most automobile manufacturers since communication, power consumption, available space and cost become important issues for a growing number of engine control units. Our contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex.

Current trends show that in future it will be essential that various kinds of applications are running on one chip. These require an efficient and flexible network on chip which is able to adapt to the demands of supported modules. This makes it necessary to think about what kind of network on chip will meet these requirements. This paper describes an approach for a reconfigurable network on chip which allows adapting the performance and topology at run-time to the demand of the application running on Xilinx FPGA.

Microcontrollers and ASICs have become a dominant part during the last years in the development of embedded applications like automotive control units. As described in our previous contribution we presented an alternative approach exploiting the possibilities of partial run-time reconfiguration of state-of-the-art Xilinx Virtex FPGAs. Our approach used a run-time system software for controlling reconfiguration and message handling. This paper presents some new extensions introducing dynamic priority measures as a first approach for adaptive reconfiguration decisions.

The power consumption of reconfigurable systems has become a fundamental aspect in designing applications. Especially for mobile systems with a limited power supply, it is necessary to identify and optimize the power loss. Moreover, it is essential to evaluate during application development time exact power trade-offs, especially including the consideration of the dynamic reconfiguration phases of corresponding devices, e.g. the Virtex-series from Xilinx. This paper discusses the exact power consumption trade-offs between the measured runtime consumption of a mapped application and the measured reconfiguration-time consumption of different dynamically (partially and completely) reconfigured applications. Moreover, the possibilities and limitations of today's available power estimation tools are discussed and compared to the exact measurements.