A 1.3mW 8-bit Two-step Time-to-Digital Converter (TDC) with 3.8-ps resolution is proposed. It combines the advantages of the SAR and Vernier TDCs to improve the resolution and the dynamic range while holding the low power. The proposed Two-step TDC cancels the time amplifier to avoid its nonlinear problem. The whole architecture consists of coarse conversion and fine conversion. The coarse conversion uses the structure of successive approximation register, and the fine conversion uses the structure of Vernier. In order to compose these two TDCs well, a residual time generating circuit and an absolute value circuit are proposed and designed. The TDC circuit conversion rate is 60MS/s. The DNL and INL are 0.46(LSB) and 2.3(LSB), respectively. The occupied area of TDC is 0.036mm 2 .

A two-step time-to-digital converter (TDC) based on digital-to-time converter (DTC) is proposed in this paper. This architecture uses DTC as delay cell, it changes DTC's delay time by adjusting the DTC's delay control words(DCW) , and sets the neighboring DTC's delay time to keep the TDC's resolution constant. The resolution can reach 1 picosecond. Two-step structure can reduce the number of flip-flops and delay cells by half, it can reduce the power consumption significantly, and the area is also decreased at the same time. This 4-bit TDC architecture has been designed and simulated in 130nm CMOS process. The power consumption is about 0.7mW; the resolution is 1 picosecond and the core area is about 0.017mm 2 .

In this paper, an 8/16× time amplifier (TA) using ring oscillator (ROSC) is presented. For a wide input range, a time register (TR) based on gated ring oscillator (GRO) is proposed which has a variable capacity and can realize the accumulation and subtraction of time. Together with the proposed double multiplication phase detector (PD), the TA is implemented, which achieves a wide input range of more than ±200ps, and programmable gain without any calibration. The gain error is less than ±4.5% in all gain modes under various process, voltage, and temperature (PVT), while consuming 477uw with a 30MHz sampling frequency. The TA has no areaintensive passive devices and occupies an area of 0.0068mm 2 in 130nm CMOS process. In addition, by adjusting the capacity of TR, a higher throughput rate or a wider input range can be selected for TA according to the actual requirement.