The article presents a novel audio zero-watermarking technique that is free of creating any watermark data in the original audio. The strategy depends on the robust features of the audio in order to generate an audio fingerprint. Primarily, the audio is divided into non-overlapping frames, and time-based, frequency-based, and structural features are obtained out of each frame. The features are then weighted on the basis of its stability to construct a very robust composite feature representation. The adaptive thresholding scheme is used to apply a binary sequence to the composite representation and the watermark data is then appended to the binary sequence to produce the final audio fingerprint. Lastly, the features extracted along with the corresponding binary sequence that acts as a label of every frame are then fed to a Random Forest (RF) classifier. The feature vectors derived when extracting the attacked audio are fed to the trained Random Forest classifier in order to reconstruct the original binary sequence during extraction. This sequence is subsequently combined with the existing fingerprint and it becomes possible to reconstruct the watermark. The results of simulations indicate that the technique preserves the original quality of the audio, but provides good resistance to numerous types of attacks, such as additive noise, filtering, MP3 compression, re-sampling and re-quantization changes, as well as time and pitch rescaling.

The Internet of Things (IoT) is transforming modern computing by enabling massive numbers of interconnected devices for smart healthcare, transportation, environmental monitoring, and industrial automation. These devices require ultra-low power consumption, compact architectures, and high reliability, since they often operate on limited energy budgets and in harsh environments. Conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology is increasingly unable to meet these demands due to scaling bottlenecks, leakage currents, high heat generation, and process variability, limiting its applicability for sustainable IoT systems. In order to address these issues, Quantum-Dot Cellular Automata (QCA) has emerged as a post-CMOS nanoscale computing paradigm in which binary information is encoded through electron configurations rather than current flow. This approach enables ultra-low energy dissipation and improved tolerance to fabrication-related defects when compared to conventional CMOS designs. In this paper, we present an original fault-tolerant 3-input majority voter (MV3) with seven quantum cells. The proposed MV3 gate exhibits 100% tolerance under the evaluated single-cell omission defect scenarios considered in this study, demonstrates fault resistance of up to 90% under extra-cell deposition conditions, and reduces power dissipation by up to 94.38% compared with the best previously reported designs. Building on this foundation, we reconstruct several MV3-based IoT processor components, including a 2:1 multiplexer, an adder, a 4-bit ALU, a 4-bit accumulator, memory, and a 4-bit CPU architecture using the proposed MV3 gate as the main logic primitive. QCADesigner and QCAPro, analyses confirm the functional correctness, thermal behavior, and energy characteristics of the proposed primitive and selected module-level circuits, while the complete 4-bit CPU provides a layout-level proof of concept for MV3-based IoT-oriented QCA processing.

Modern computing relies on very-large-scale integration (VLSI)-integrated systems for higher-dense, high-speed integration of complex digital subsystems with more energy-efficient, reliable, and compact systems. Quantum systems are emerging technologies supporting next-generation computing workloads through quantum/reversible gates. Sequential design synthesis with optimized parameters has been explored in the era of quantum technology. A reversible/quantum design flow requires optimized building blocks for storage and control to enable efficient integration and reuse of systems. A parity-preserving reversible sequential circuit is attractive for integrated quantum/reversible platforms because it embeds a low energy dissipation, inherent error-indication property, while maintaining unique input reconstruction capability. We propose a compact 5 & times; 5 parity-preserving reversible D-gate as a core design for reusable sequential circuit designs. A transformation-based Miller synthesis is used to structure the novel D-gate, which is then mapped to the NCV library and optimized via simplification/templates, which reduces the quantum cost (QC) to 7 (58.82%). The D-gate is used to synthesize low-overhead D-FFs, counters, and shift registers. The proposed D-FF designs achieve QC = 7, garbage output (GO) = 2, constant input (CI) = 2, and gate count (GC) = 1. These values match the lowest QC reported among the selected D-FF baselines while reducing GO, CI, and GC relative to several prior designs. Compared with the best previous one, the proposed designs reduce QC by 22.22%, GO by 33.33%, CI by 33.33%, and GC by 50.00%. Further design of various circuits, such as up/down counters, Johnson counters, and shift-register families are developed. The proposed SIPO design achieves QC = 28, GO = 6, CI = 8, and GC = 4, reducing QC by 41.67%, GO by 40.00%, and GC by 50.00% compared with the representative prior shift register, while CI remains unchanged. We use IBM-Qiskit quantum simulation to validate qubits in the D-FF design. Furthermore, a noise-aware D-FF simulation is performed in the IBM-Qiskit environment to examine the behavior of the proposed circuit under selected quantum noise models. As a result, proposed parity-preserving sequential blocks can be used as elements for quantum and reversible computing platforms integrated into complex systems.

Quantum-dot cellular automata (QCA) technology has gained attention lately due to its ability to reduce energy dissipation and minimize circuit area. However, the existing research shows that a critical challenge arises from the lack of circuit resistance in QCA systems when confronted with defects. This issue directly impacts circuit stability and output generation. Moreover, the 3-input majority gate (MV3) is a foundational component within QCA circuits, making its improvement crucial for developing fault-tolerant circuits. One approach is to design MV3 that incorporates essential quantum cells within a single clock cycle. Thus, this paper presents a unique cellular structure for the MV3 gate, utilizing simple quantum cells. The proposed gate, comprising only twelve cells, serves as a building block for QCA circuits. It boasts several key features, including low power consumption, efficient output polarity (± 9.93e00−1), and high reliability. Furthermore, to show the efficiency of the suggested gate, it is employed in realizing a 2:1 multiplexer and a full adder/subtractor. Lastly, the proposed MV3 gate is utilized to develop a simultaneous multi-logic gate which is producing several vital digital circuits, such as AND, OR, NOT, NAND, Copy, Subtractor, and Adder. The circuits are designed using QCADesigner and QCAPro, with power estimation included in the process. The comparative analysis reveals that the proposed structures significantly enhance the trade-off between complexity, fault tolerance, and power consumption compared to previous designs.

Three-dimensional Network-on-Chip (3D-NoC) is an efficient solution to overcome communication limitations in complex System-on-Chip (SoC) architectures. However, challenges such as increased temperature, traffic congestion, and link wear-out significantly impact network performance and lifespan. In this study, we propose an adaptive routing algorithm named CTWR (Congestion, Temperature and Wear-aware Routing), which simultaneously considers temperature, congestion, and wear-out while utilizing both intra-layer and inter-layer routing approaches to enhance network performance. The algorithm employs a dynamic approach to assess the real-time status of vertical links to control and reduce wear-out, selecting paths that mitigate thermal hotspots, balance traffic distribution, and extend the lifespan of interconnects. Extensive assessments and simulations performed under diverse traffic scenarios and multiple vertical link or elevator layout configurations indicate that the CTWR algorithm outperforms ETW, EF, HE, and Nezarat routing methods in reducing average packet delay by 92.71 %, 67.84 %, 56.33 %, and 26.91 %, respectively. Furthermore, our proposed approach enhances average network throughput by 9.88 %, 4.38 %, 2.64 %, and 1.66 % compared to these methods. Thermal analysis of the chip surface also reveals a lower overall temperature and a more balanced heat distribution than competing techniques.

Quantum computing has attracted increased attention in recent years owing to substantial advancements in quantum algorithms and system architecture. Quantum algorithms are implemented using quantum circuits. These circuits include an intrinsic reversibility and often have a substantial Boolean component that requires synthesis. A crucial characteristic of reversible circuits is the preservation of parity. Parity-preserving logic is a category that maintains the parity of both inputs and outputs, facilitating the detection of permanent and transient errors. Multiplier circuits are essential components in digital computing systems, playing a crucial role in the development of various hardware, including arithmetic circuits. This paper first introduces a novel block based on a transformationbased synthesis technique from the elementary quantum gates. Then it proposes a distinctive 2x2 parity-preserving reversible quantum Vedic multiplier based on the recommended block and prior gates. In addition, further designs of Vedic multipliers are provided, encompassing 4-bit, 8-bit, and 16-bit configurations. We illustrate that our design brings superior outcomes regarding quantum cost (QC), constant inputs (CI) count, CNOT-V/V+ count, garbage outputs (GO) count, and gate count (GC) in comparison to earlier designs. This study achieves an average decrease of 23.09%, 37.51%, 37.51%, 54.89%, and 19.38% in QC, CI, GO, GC, and CNOT-V/V+ count, respectively. Furthermore, all suggested circuits undergo appraisal and validation within the IBM quantum laboratory.

Digital image processing (DIP) is the ability to manipulate digital photographs via algorithms for pattern detection, segmentation, enhancement, and noise reduction. In addition, the Internet of Things (IoT) acts as the eye and system for all DIP in various applications. It can possess a camera or another image sensor in order to capture real-time data from its environment. All vital data is processed by image processing in such a way that it recognizes the object, detects an anomaly, and automatically decides in real-time. In addition, in an IoT system, the median filter is the technique used for noise reduction by substituting the value of the pixel with the central value of the surrounding pixels. It provides speed and efficiency for quick analysis in all IoT systems. However, the images can get corrupted, especially in resource-constrained IoT devices with small cameras, because of random glitches. Moreover, using new quantum technology like atomic-scale silicon dangling bond (DB) logic circuits, which have advanced in fabrication and become a strong contender for field-coupled nano-computing, can solve previous problems in IoT systems. In this article, we propose a unique quantum CSM based on two new proposed Mux and De-mux. The proposed CSM can be used for computational circuits like median filter circuits (MFC) in a wide range of digital circuits, specifically IoT devices. The proposed design is verified and validated using the powerful SiQAD tool. When comparing CSM to the newest designs, the suggested quantum circuit uses 85% less energy and takes up 61% less area.

One of the basic challenges in high-density integrated circuits is loss of power consumption, which is caused by presence of transistors in circuits and causes the temperature of the circuit to increase. The design of digital circuits in a reversible way can be used as one of efficient approaches to solve this challenge. In addition, the design of parity-preserving reversible circuits can be very effective in detecting faults in circuits. Dividers are used as one of the most widely used circuits in digital computing systems. Divider circuits include an adder, a multiplexer and two sequential register and parallel-in to parallel-out left shift register circuits. This paper is presented a new and efficient design of a parity-preserving reversible non-restoring divider. For this purpose, first, a parity-preserving reversible D-latch is proposed. second, a parity-preserving reversible n-bit register is presented using the proposed reversible D-latch. Third, a parity-preserving reversible (n+1) bit shift register using the proposed reversible D-latch and other reversible gates is proposed. Finally, a parity-preserving reversible n bit divider is developed based on the non-restoring algorithm. The results of comparisons show that the proposed circuit is superior in terms of evaluation criteria of reversible circuits such as quantum cost, number of constant inputs and number of garbage outputs compared to previous works.

The importance of using Brain-Computer Interface (BCI) systems based on electro encephalography (EEG) signal to decode Motor Imagery(MI) is very impressive because of the possibility of analyzing and translating brain signals related to movement intentions. This technology has many applications in the fields of medicine, rehabilitation, mind-controlled computers and assistive technologies. Despite significant progress in EEG-based BCI systems, there are challenges such as signal noise, low decoding accuracy, instability and changeability of signals, etc. To address these limitations, this article presents a new approach to classify MI from EEG signals with the help of synergistic Hilbert-Huang Transform(HHT) as pre-processing, Permutation Conditional Mutual Information Common Space Pattern (PCMICSP) as features and optimized back propagation neural network(BPNN) based on Honey Badger Algorithm(HBA) as classifier. Using the ergodicity of the HBA, along with chaotic mechanisms and global convergence, this approach encodes and optimizes the weights and thresholds of a BPNN. Initially, a comprehensive optimal solution is obtained through the honey badger algorithm. Subsequently, this solution is further refined to reach a more precise optimal state by introducing chaotic disturbances. The proposed method efficiency was confirmed through experimental analysis on a set of data of benchmark that is generally accessible of EEGMMIDB (imagery database or motor movement of EEG). Our experimental analysis outcome showed that mechanism development is important. Now, two EEG signal levels were taken into consideration: the first being an epileptic and the other being non-epileptic. The presented technique generated a max accuracy of 89.82% in comparison with other methods.

Atomic Silicon Dangling Bond (ASDB) is a promising new nanoscale technology for fabricating logic gates and digital circuits. This technology offers tremendous advantages, such as small size, high speed, and low power consumption. As science and technology progress, ASDB technology may eventually replace the current VLSI technology. This nanoscale technology is still in its early stages of development. Recently, many computing circuits, such as full-adder, have been designed. However, these circuits have a common fundamental problem; they consume a lot of energy and occupy a lot of area, which reduces the performance of complex circuits. This paper proposes a novel ASDB layout for designing an efficient full-adder circuit in ASDB technology. Moreover, a four-bit ASDB ripple carry adder(RCA) is designed using the proposed ASDB full-adder. The proposed ASDB fulladder not only improves the stability of the output but also surpasses the previous works, in terms of energy and accuracy,by 90% and 38%, respectively. Also, it has very favorable conditions in terms of occupied area and is resistant to DB misalignment defects.

The proposed approach in this study introduces a comprehensive audio steganalysis scheme that integrates quantum signal processing with machine learning techniques. This method employs the quantum Fourier transform on the Quantum Representation of Digital Signals (QRDS) to extract statistical features from the second-order derivatives of the audio spectrum. These features are derived by analyzing the rate of change in the gradient of the quantum spectrum, providing valuable insights for identifying steganographic content, concealed within the audio data. The statistical analysis of these features includes the quantum spectral center (QSC), quantum spectral bandwidth (QSB), quantum spectral flatness measurement (QSFM), and quantum spectral crest factor (QSFC). The extracted features are then input into a multilayer quantum neural network that utilizes simple quantum gates, thereby reducing the algorithm's complexity and the time required for training and testing. The classification algorithm, applied by this neural network, can distinguish between clean and stego audio datasets, with an accuracy exceeding 96 %. It outperforms existing methods in both efficiency and accuracy.

Quantum watermarking serves as a pivotal technique for data concealment within quantum networks; facilitating secure communications by subtly embedding confidential data, such as private numbers, audio and images into digital carrier signals. This approach aims to maintain the integrity of quantum transmissions, while exerting minimal influence on the host signal. One aspect of watermarking, known as "echo hiding," involves integrating watermark data into a host audio signal, in the form of delays; also known as echoes. The bipolar echo hiding method introduces two symmetrical echoes with distinct delays. These parallel echoes are generated by echo kernels, with delays d_0 and d_1 and amplitude amplification coefficients, α_1 and α_2 . Separate quantum echoes are created and added to the original signal to accommodate | 0 . or | 1 . qubits. The bipolar echoes mitigate the distortion caused by the echo in the watermark signal, effectively cancelling out each other’s impact and enhancing signal transparency. In the extraction phase, the difference between the watermark and main signal is calculated and compared with the sum of the echo kernel. These sets are marked to recognize the watermark data. All quantum circuits have been simulated and demonstrated at the nanoscale. With an identical capacity (512 qbps), the bit error rate and signal-to-noise ratio of the proposed method have been compared with other quantum methods. The reported transparency of this method is 70.46 dB. A notable feature of this method is the robustness of the watermark signal against attacks.

Quantum computers provide considerable potential to enhance computing technology, anticipated to surpass conventional computers by resolving intricate challenges that existing systems cannot tackle. They use quantum algorithms for improved performance and depend on reversible computations based on quantum physics and linear algebra. In contrast to traditional computing, which may include irreversible processes, quantum computing relies on unitary operations that are fundamentally reversible. The parity-preserving feature enables the identification of both permanent and transient defects within circuits. The parity-preserving feature ensures that the input and output states are equal in reversible circuits. Vedic multipliers offer a crucial foundation in the design and implementation of digital circuits, recognized for their speed, efficiency, ease of calculations, reduction of errors, and broad applicability. Prior investigations of quantum Vedic multipliers have faced obstacles like elevated Quantum Cost (QC), substantial Garbage Output (GO), Constant Input (CI), augmented Gate Count (GC), and CNOT-V/V+ count, resulting in more resource use and implementation intricacy. These inefficiencies hinder the scalability and feasibility of quantum multipliers in high-performance computing applications. A proposed solution to these issues is to introduce a cost-effective, parity-preserving reversible quantum block synthesized through an established method that produces a network list of multi-controlled Toffoli (MCT) gates. This Toffoli-based network is then optimized using various techniques, ultimately transforming it into a network of fundamental quantum gates. This approach decreases quantum expenses, eliminates unnecessary outputs, and enhances quantum gate efficiency. Integrating this innovative technique into the reversible quantum Vedic multipliers offers a more efficient, cost-effective, and scalable solution than current approaches. All proposed designs, such as a half adder-subtractor, a ripple carry adder (RCA), and two-bit and four-bit Vedic multipliers, are suggested based on functional blocks and pre-existing components. The suggested structures undergo evaluation in comparison to existing state-of-the-art procedures, demonstrating their cost-effectiveness. The observed average savings for two-bit and four-bit Vedic multipliers, with respect to QC, number of CNOT-V/V+ count, GO, CI, and GC, are 20.01%, 19.38%, 37.51%, 37.51%, and 54.89%, and 22.71%, 18.78%, 27.23%, 31.10%, and 42.38%, respectively when compared to previous studies. Furthermore, all suggested circuits are evaluated and confirmed using the IBM quantum laboratory.

This paper addresses critical issues such as leakage and heating in Internet of Things (IoT) circuits by exploring alternatives beyond CMOS technology. Atomic silicon dangling bond (ASDB) technology emerges as a promising substitute for executing nanoscale logic circuits, particularly for IoT applications requiring compactness, efficiency, and energy optimization. We propose a Hammer-shaped design for ASDB basic gates to enhance circuit stability and optimality, which is vital for the reliable operation of IoT systems. we demonstrate a new ASDB one-bit comparator circuit to highlight the practical application of the proposed design, which is crucial for real-time data processing in smart homes, industrial automation, health monitoring, connected vehicles, environmental sensors, and smart grids. By integrating high-performance comparator circuits, IoT networks gain improved accuracy and reduced latency, enabling advancements in energy management and wearable electronics. Simulation results highlight significant improvements, including a 33% enhancement in occurrence, 27.% in energy efficiency, 56% resistance to DB omission, and 51% in extra DB deposition.

Quantum-dot Cellular Automata (QCA) is a computational technology that can be used to construct nanoscale circuits. Nowadays, this technology is a good alternative for CMOS technology due to features such as high speed, low occupied area and low power consumption. Mmemory is utilized as one of the basic elements in digital circuit design hence the design and optimization of high-speed RAM memory cells have become one of the most attractive research areas; in the realm of QCA. In this paper, we present a comprehensive investigation on RAM memories. For this purpose, the proposed schemes in terms of functionality, the number of cell consumption, and latency are implemented and compared using QCA Designer software. The results show that some of the proposed schemes show better performance in terms of parameters such as occupied area and delay. Nevertheless, they are still suffering from less stability; hence introducing an optimum scheme is infeasible.

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Quantum-dot Cellular Automata (QCA) has emerged as a revolutionary technology for nano-scale computing circuits and a promising alternative to conventional transistor-based technologies. However, the susceptibility to defects during circuit synthesis is a pivotal challenge, undermining its potential. This study seeks to introduce an innovative and robust fault-tolerant 3-input majority voter gate comprising 16 simple cells. The primary objective is to enhance the gate's resilience against two specific defects: one-cell omission and extra-cell deposition. Preliminary assessments indicate that the introduced gate achieves remarkable tolerance rates of 100% for one-cell omission and 89.47% for extra-cell deposition defects. A comprehensive evaluation is used based on the QCADesigner 2.0.3 simulator to validate the gate's performance, supplemented by physical proofs. Furthermore, leveraging the novel gate structure, this paper extends its application to the design of fault-tolerant flip-flops and multiplexer circuits. These building blocks are then employed to construct three distinct fault-tolerant sequential circuits.

Quantum-dot Cellular Automata (QCA), is a contemporary nanotechnology for manufacturing logical circuits which brings less power consumption, smaller circuit size, and faster operation. In this technology, logical gates are composed of nano-scale basic components called cells. Each cell consists of four quantum-dot arranged in a square pattern. Diagonal arrangement of two extra electrons resembles two logical states 0 and 1. Majority gate and inverter gate are considered as the two most fundamental building blocks of QCA. The effect of cells on their neighbor cells enables designing more diverse circuits. Multiplexer is a key component in most computer circuits. Researchers have presented various QCA designs for multiplexers since the introduction of QCA. In this research all presented designs are simulated in QCA Designer Version 2.0.3 and investigated from different aspects such as number of cells, size, types of components used in circuit, number of layers, and number of cycles for producing output.

As CMOS technology approaches its physical and technical limits, alternative technologies such as nanotechnology or quantum computing are needed to overcome the challenges of lithography, transistor scaling, interconnects, and miniaturization. This article introduces a novel nanotechnology that uses atomic-scale silicon dangling bonds (ASDB) to create high-performance, low-power, nanoscale logic circuits. DBs are atoms that can form basic logic gates on a silicon surface using a scanning tunneling microscope device. ASDB can also be an alternative to the existing complementary metal oxide semiconductor (CMOS) technology. The article also proposes a new bar-shaped pattern to design gates and logic circuits with ASDB nano tecnolgoy. The bar-shaped pattern improves the reliability of the output, reduces the area and power consumption, and solves the problem of interatomic energy effects of ASDB. The article demonstrates the efficiency of the bar-shaped pattern by implementing two-input gates such as AND, NAND, OR, NOR, XOR, XNOR, and a 2:1 multiplexer with ASDB. The article also uses a powerful tool called SiQAD to simulate and verify the performance of the proposed structures with ASDB. According to the simulation results, the proposed logic gates are more energy efficient, stable, and compact than the previous structures. They consume 35

Today, Complementary Metal-OxideSemiconductor (CMOS) technology faces critical challenges, such as power consumption and current leakage at the nanoscale. Therefore, Atomic Silicon Dangling Bond (ASDB) technology has been proposed as one of the best candidates to replace CMOS technology; due to its high-speed switching and low power consumption. Among the most important issues in ASDB nanotechnology, output stability and robustness against possible faults may be focused. This paper first introduces a novel P-shaped pattern in ASDB, for designing stable and robust primitive logic gates, including AND, NAND, OR, NOR and XOR. Then, two combinational circuits, half-subtractor and full-subtractor, are proposed by the proposed ASDB gates. The simulation results show high output stability as well as adequate robustness, against various defects obtained by the proposed designs; on average, they have improvements of more than 56% and 62%, against DB omission defects and extra cell deposition defects; respectively. Also, the results of the investigations show that the proposed circuits have been improved by 65%, 21% and 2%, in terms of occupied area, energy and occurrence, respectively; compared to the previous works.