We recently reported communication up to 60Gb/s between digital superconductor chips mounted on a passive carrier, using a novel driver circuit that produces a double-flux-quantum pulse. Here, we answer various practical questions pertaining to chip-to-chip and on-chip communication in greater detail. On-chip, the traditional single-flux-quantum driver is adequate, although margins and bit error rate degrade significantly at the microstrip resonance frequency. Chip-to-chip, using the double-flux-quantum driver, shows little frequency dependence, in spite of 13% reduction of signal current in the chip-to-chip transitions. Appropriate microstrip impedance is in the range 4-8 Ohm for a 4kA/cm(2) Josephson junction IC process. Data includes bit errors rates for pseudo-random data in the range 3-27 Gb/s.

Superconductor digital devices using single-flux-quantum (SFQ) data encoding offer higher speed at lower power than any other integrated circuit technology. For this very reason, interconnect is challenging. We report SFQ data transfer between chips flip chip mounted on a passive microstrip carrier. The flip-chip structure achieves bandwidths greater than 250 GHz. Unlike previous designs, our signal lines are terminated at both ends; this is accomplished using a driver that produces a double-flux-quantum signal. We measured the circuit for pseudorandom data in the range of 10–60 Gb/s. Bit error rates are measured down to 1E−10 and extrapolate to negligible values. The signal power on the microstrip is only 30 nW at 60 Gb ps.

We have developed a cryogenic probe and cryostat system to test both active and passive superconducting devices and circuits up to microwave frequencies at variable temperatures. Our system consists of two basic parts: the cryostat and the matching probe. The cryostat is a unique, very efficient, variable temperature, flow-type cryostat, where we control temperature without electrical heaters. It is magnetically shielded and allows rapid testing between 4.2 K and room temperature. Probes developed for this cryostat have a larger number of shorter cables than standard dip-type probes. They are designed to test chips or chip assemblies without additional packaging. Chips or chip assemblies can be quickly mounted and dismounted from a fixed spring-contact assembly. Each probe has 56 wide-bandwidth signal cables. We have repeatedly used these probes for testing both active and passive superconducting integrated circuits up to 20 GHz. The probe and cryostat combination provides a testing capability that is simultaneously high frequency, dc magnetic shielded, has variable cryogenic temperature, and quick turnaround.

Building computers with petaflop (10(15) operations per second) capability will require packaging technology capable of handling 10's of Gbit/second per data line, with literally millions of lines. Speed, power, and packing density requirements strongly suggest that the computational core of such a machine will rely on superconducting elements and wiring. We present the rep-level system design and preliminary experiments for cytogenic, high density packaging for such a next generation machine.Starting from the basic architectural requirements for a multi-threaded, multi-processor design, we are developing the key packaging technologies including flip-chip chip bonding and GHz cabling. To minimize interconnect inductance, we have demonstrated an indium-tin solder reflow process producing flip chip bonds less than 2 microns high. For silicon-to-silicon bonding, the process is quite robust. We have formed 6,400 connections on a 5-mm single chip without failure. The bumps support data transfer at 10 Gbit/second in a cryogenic environment with clean "eye" diagrams. The process is amenable to rework for chip replacement.We are also investigating specialized high-speed cabling for the cryogenic environment. The cables must simultaneously display low dispersion and low attenuation for 10 Gbit/second digital signals, while minimizing thermal conduction from warm to cold ends. We have optimized layer thicknesses and construction of polyimide/copper microstrip cables. We will present electrical, thermal, and mechanical measurements.

We have built and operated a wide band electrically small active antenna consisting of a YBa/sub 2/Cu/sub 3/O/sub 7/ half-loop over ground plane antenna, an LTS (niobium) 200 element DC SQUID array amplifier, and low-noise cryogenic GaAs buffer amplifier. These components were integrated with a liquid He flow cryostat into a portable stand-alone package. Measurements of active antenna response from 50 to 500 MHz were made using a transverse electromagnetic cell to illuminate the half-loop antenna. At frequencies below the observed antenna resonance (250 MHz) the active antenna response is flat thereby exhibiting wide band gain.

The authors report the design, fabrication and test results of a 12-bit NbN SFQ counting A/D converter operating at 9 to 10K and its insertion into a test IR focal plane array sensor system. The NbN IC is based on a linearized SQUID front-end which generates SFQ pulses at a frequency proportional to the signal. A gated SFQ counter integrates the signal over the sample time and the data is driven off chip through a serializing latching voltage state logic (MVTL) output shift register. The TRW A/D converter chip has been packaged and inserted into an IR focal plane array sensor test facility, or test bed, at the NASA Jet Propulsion Laboratory. The entire system has been successfully demonstrated producing IR images at 100frames/s with the NbN A/D converter operating at 9K, dissipating 0.3mW. Performance of the A/D converter chip, the package including magnetic shielding and medium/high speed signal I/O, and the integrated test bed system are discussed.

As complexity of superconducting digital systems increase, the need for multi-chip modules and a reliable, high bandwidth attachment scheme for superconducting die becomes more and more critical. We have developed a flip chip die attach process for Low Temperature Superconducting (LTS) chips using InSn reflow soldering. Using standard reflow techniques, we create highly reproducible, uniform 14 micron-high solder bumps on gold-defined pad regions. Subsequent alignment, compression, and reflow soldering produce reliable, low inductance connections with high yield. The short interconnect distance of 5-7 /spl mu/m results in low enough inductance to support multi-GHz chip interconnect at low impedance. We have successfully tested and thermally cycled flip chipped die over many temperature cycles to liquid helium temperatures with no failures. We will report on successful attachment, testing, and rework of superconducting circuit chips. Specifically, we present data on solder bump uniformity, yield, electrical and thermal characteristics, reworkability, and reliability under repeated thermal cycling.

For the purpose of testing and demonstrating the practical implementation of TRW's superconducting analog to digital converter (ADC) in an imaging system, JPL is developing a test-bed which the superconducting ADC is integrated within a mid-infrared camera. This paper describes the overall system architecture with some emphasis on the design challenges that have been overcome in developing the test-bed. Upon completion, the test-bed will be capable of characterizing the performance of various types of cryogenic ADCs within a realistic imaging application. Of particular note, the system can accommodate digitization rates of up to 40 million pixels per second with a resolution of up to 24 bits per pixel. Additionally, the acquisition electronics can handle a single bit-serialized digital data stream from the ADC. This is key in minimizing the thermal insulation complications introduced by having multiple output lines. On the receiving end of the data stream, the data acquisition computing system has been designed to have the necessary throughput speed and capacity to continuously acquire a few thousand image frames without missing any data. Performance system required computing processed images for real-time display

High temperature superconductors (HTS) promise to achieve electrical performance superior to that of conventional electronics. For application in space systems, HTS systems must simultaneously achieve lower power, weight, and volume than conventional electronics, and meet stringent space qualification and reliability requirements. Most effort to date has focused on passive RF/microwave applications. However, incorporation of active microwave components such as amplifiers, mixers, and phase shifters, and on-board high data rate digital signal processing is limited by the power and weight of their spacecraft electronic and support modules. Absence of data on active HTS components will prevent their utilization in space. To validate the feasibility in space of HTS circuits and components based on Josephson junctions, we need to demonstrate HTS circuits and critical supporting technologies, such as space-qualified packaging and interconnects, closed-cycle cryocooling, and interface electronics. This paper describes the packaging, performance, and space test plan of an integrated, space-qualified experimental package consisting of HTS Josephson junction circuits and all the supporting components for NRL's high temperature superconductor space experiment (HTSSE-II). Most of the technical challenges and approaches are equally applicable to passive and active RF/microwave and digital electronic components, and this experiment will provide valuable validation data.

The use of high temperature superconductor (HTS) electronics in space will achieve superior electrical performance at substantially lower power, volume, and weight than conventional electronics. This requires both HTS circuits and their supporting technologies, such as space-qualified packaging and interconnect, closed-cycle cryocooling, and interface electronics. To validate the feasibility of HTS digital circuits in space, we developed and delivered an integrated space-qualified experimental package consisting of digital HTS circuits and all the supporting components for the High Temperature Superconductor Space Experiment (HTSSE II). This paper describes the packaging, performance, and space test plan for TRW’s HTS digital cryogenic experiment.

Demonstrating superconductive logic circuits at high speeds is crucial in gaining acceptance by potential users. We are taking an integrated approach toward demonstrating the potential of such circuits. Issues addressed include the effects that layout have upon a circuit and gate (particularly in scaling down the size of gates to increase density), testing limitations, designing for minimum crosstalk and ground ripple, and fundamental limitations to gate performance. In this paper, we report our progress in resolving and understanding these issues. Circuits such as shift registers were used to understand the influence of layout on performance, circuits such as gate chains and punchthrough detectors to explore fundamental gate limitations. We also report on signal processing circuits of several hundred gates tested at clock frequencies up to several hundred MHz and the relationship between these results and the fundamental gate performances.<>

Experiments are performed on an HTS transmission line fabricated with a series array of Josephson junctions. We have determined the phase shift mechanism and have measured the magnitude of the phase shift of wide junctions. A qualitative model of the phase shift mechanism has been developed which explains the effects of applied magnetic fields. (C) 1993 John Wiley & Sons, Inc.

Shifting of the energy gap of a Nb Josephson junction under direct optical illumination was measured. The response is linear with optical input power over more than five orders of magnitude and is nearly independent of temperature from 4 to 8 K. The rise time of this signal is faster than the 2- mu s rise time of the chopped light signal. These direct signals are 500 to 1500 times larger than those obtained when the same optical power is focused elsewhere on the substrate. This enhanced direct response is interpreted as resulting from thermal isolation of the Josephson junction from the substrate due to thermal boundary resistance.<>

Recent work at TRW on ultra-thin film detectors (similar to 100 angstrom) of NbN have demonstrated good response to visible and infrared radiation. To be viable for imaging sensors, increased sensitivity is required. Increasing the coupling efficiency of the radiation field to the detectors is one method to improve detector performance. This can be achieved with planar antennas. We describe such a device which is also compatible with typical focal plane array imaging systems. We observed an enhancement in the signal-to-noise ratio by 32 dB when comparing antenna coupled detectors to area detectors (e.g. meandering lines). Additionally, we observed a polarization selectivity of about 13 dB to linearly polarized light, which can provide additional discrimination.

We have deposited thin films of YBa2Cu3O7 (YBCO) on LaAlO3 substrates previously textured with submicron features by the use of "natural lithography" (the use of monolayers of polystyrene microspheres as lithographic masks)1. This weakens the superconducting properties due to reduced connectivity in the film. Devices fabricated using localized textured regions have shown Josephson coupling. Weak links have shown Shapiro steps at the expected voltage intervals. Magnetic field induced modulation in the detected RF voltage with the geometrically correct periodicity has been observed in RF SQUIDs over a limited temperature range.

A variety of techniques to reproducibly engineer microbridges in high-quality epitaxial YBCO films exist. A report is presented on two such techniques that have resulted in high-yield processes for fabricating both DC and RF SQUIDs operating at temperatures as high as 82 K. The results of these devices (step-edge microbridges) and focused-ion-beam microbridges) are compared with those of several other structures under investigation by other researchers

Measurements of SNS planar microbridges made from high-quality in situ sputtered YBCO films were made. The devices were fabricated using single superconducting films with a patterned gap bridged by sputter-deposited silver. A number of devices exhibit supercurrents and microwave-induced steps in the current-voltage characteristics. In the best devices the normal state resistance is consistent with expected values. The consequences of the anisotropy of YBCO and the effects of various fabrication techniques on device performance and yield are discussed

The very likely existence of dispersion in the 5f spectra obtained in angle-resolved photoemission at 300 K raises questions about the localized nature of 5f electrons at room temperature.