Efforts to fabricate superconducting wires made of YBa2Cu3O7 (YBCO) on La2Zr2O7 (LZO) buffered and biaxially textured Ni-5 at.%W (NiW) are described. Wires were manually shaped from LZO buffered NiW tapes. Different diameters were produced: 1.5, 2 and 3 mm. The wires were further covered with YBCO grown by metal organic chemical vapor deposition (MOCVD). We developed an original device in which the round substrate undergoes an alternated rotation of 180° around its axis in addition to a reel-to-reel translation. This new approach allows covering the whole circumference of the wire with a YBCO layer. This was confirmed by energy dispersive x-ray spectroscopy (EDX) analysis coupled to a scanning electron microscope (SEM). For all wire diameters, the YBCO layer thickness varied from 300 to 450 nm, and the cationic composition was respected. Electron backscattering diffraction (EBSD) measurements were performed directly on an as-deposited wire without surface preparation allowing the investigation of the crystalline quality of the film surface. Combining EBSD with XRD results we show that YBCO grows epitaxially on the LZO buffered NiW wires. For the first time, superconductive behaviors have been detected on round substrates in both the rolling and circular direction. Jc reached 0.3 MA cm−2 as measured at 77 K by transport and third-harmonic detection. Those preliminary results confirm the effectiveness of the MOCVD for complex geometries, especially for YBCO deposition on small diameter wires. This approach opens huge perspectives for the elaboration of a new generation of YBCO-based round conductors.

We have studied the oxidation of embedded SiGe mesas on SOI in order to co-integrate planar high Ge enriched mesas and Si mesas in the same wafer. We show that oxidation of such structure by local Ge condensation technique leads to non-uniform areas close to mesa sidewalls. Because oxidation kinetic seems to be lowered at a certain point, and since oxidation kinetic is assumed to be stress-dependent, we propose to act on the different sources of strain to counterbalance the difference in oxidation kinetic. In one hand, strain induced by the growth of SiO 2 is removed by alternation of SiGe oxidation and SiO 2 removal during the whole process. On the other hand, the nitride oxidation mask is deposited with compressive or tensile intrinsic stress to study its influence on the induced strain in the SiGe mesa. We show that by choosing the right value of intrinsic stress in the nitride, uniform SiGe mesa with high Ge content could be achieved.

Detection and quantification of biological species are critical to many areas of health care and life science. A method using the variation of the electrical properties as a function of charged bio-molecules grafting onto a sensitive substrate processed as a semi-conductor oxide thin film is presented. It is shown that a pure and doped SnO2 thin film can be used as the sensitive element. The sensitivity evolution as a function of the film microstructure, composition and resistivity is studied. It is shown that dense and conductive films are less efficient. The relation between the microstructure and the sensitivity is discussed.

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.