The authors report on measurements of the phase coherence time, tau phi , as determined from the measurement of weak negative magnetoresistance in narrow pinched Si accumulation layers. Under favourable bias conditions, one-dimensional quantum interference and electron interaction corrections to the conductivity are found. The phase coherence length is then best described in terms of the 1D Nyquist phase-breaking mechanism, with a Landau-Baber (pure metal limit) component which retains its 2D form.

The temperature dependence of the conductivity in uniaxially stressed Si(100) metal-oxide-semiconductor field effect transistor inversion layers in the weakly localised regime has been measured for temperatures from 1.2K to 4.2K. The results show a strong linear increase in conductivity with decreasing temperature. The application of uniaxial stress is shown to increase or decrease the percentage change in conductivity over the temperature range depending on the initial Fermi level at zero stress.

The transverse conductivity sigma xx' of uniaxially stressed Si(100) inversion layers has been measured at T=0.36 K. The initial application of uniaxial stress leads to an increase in valley splitting and a reduction of conductivity maxima. At high stresses, on the other hand, conductivity peaks were observed to increase and to merge with increasing stress. At intermediate stresses, the conductivity peak movements can be explained by assuming the presence of a subband-subband electron exchange interaction.

Piezoresistance measurements have been obtained on narrow polycrystalline-silicon-gated silicon field-effect transistors. From the anomalous structure observed on the piezoresistance traces it has been deduced that large compressive intrinsic edge stresses are present in these devices. These are estimated from the experimental data to be approximately 180 N mm-2, in reasonable agreement with a theoretical calculation based on a model proposed to explain the presence of such large stresses.

Measurements of the Hall (ρxy) and transverse (ρxx) resistivities in narrow polycrystalline silicon-gated Si(100) field-effect transistors have been obtained. The measurements were carried out both with and without externally applied uniaxial stress. Analysis of the results suggests the presence of large compressive intrinsic edge stresses. A model based on device fabrication is developed to explain the presence of these edge stresses.