Remote epitaxy enables high-quality epitaxial growth across large lattice and thermal expansion mismatches by leveraging the electrostatic potential of polar substrates in conjunction with two-dimensional (2D) interlayers. A clear understanding of interfacial thermal transport in such systems is essential to evaluate its potential for heterogeneous integration. To date, however, the interfacial thermal conductance (ITC) of remote epitaxy interfaces has not been experimentally determined, and the mechanisms by which 2D interlayers and electrostatic interactions affect phonon transport remain poorly understood. Here, AlN was heterogeneously integrated onto a graphene-coated SiC substrate via remote epitaxy. Nonequilibrium molecular dynamics (NEMD) simulations were combined with time-domain thermoreflectance (TDTR) measurements to elucidate how electrostatic interactions regulate phonon transmission and to establish structure-property relationships governing interfacial thermal transport in remote epitaxy. The results reveal that, despite the presence of a 2D interlayer, the ITC remains high (similar to 136 MW & centerdot;m(-2)& centerdot;K-1), which is attributed to improved crystalline quality near the interface and enhanced interfacial binding energy induced by electrostatic interactions. This work provides critical insights into the interfacial thermal transport mechanisms of remote epitaxy and highlights the pivotal role of electrostatic interactions in enabling efficient heat transfer across heterogeneous interfaces.

Liquid biopsy of cancers, detecting tumor-related information from liquid samples, has attracted wide attentions as an emerging technology. Our previously reported large-area PERFECT ( P recise- E fficient- R obust- F lexible- E asy- C ontrollable- T hin) filter has demonstrated competitive sensitivity in recovering rare tumor cells from clinical samples. However, it is time-consuming and easily biased to manually inspect rare target cells among numerous background cells distributed in a large area ( Φ ≥ 13 mm). This puts forward an urgent demand for rapid and bias-free inspection. Hereby, this paper implemented deep learning-based object detection for the inspection of rare tumor cells from large-field images of PERFECT filters with hematoxylin-eosin (HE)-stained cells recovered from bronchoalveolar lavage fluid (BALF). CenterNet, EfficientDet, and YOLOv5 were trained and validated with 240 and 60 image blocks containing tumor and/or background cells, respectively. YOLOv5 was selected as the basic network given the highest mAP@0.5 of 92.1%, compared to those of CenterNet and EfficientDet at 85.2% and 91.6%, respectively. Then, tricks including CIoU loss, image flip, mosaic, HSV augmentation and TTA were applied to enhance the performance of the YOLOv5 network, improving mAP@0.5 to 96.2%. This enhanced YOLOv5 network-based object detection, named as BALFilter Reader, was tested and cross-validated on 24 clinical cases. The overall diagnosis performance (~2 min) with sensitivity@66.7% ± 16.7%, specificity@100.0% ± 0.0% and accuracy@75.0% ± 12.5% was superior to that from two experienced pathologists (10–30 min) with sensitivity@61.1%, specificity@16.7% and accuracy@50.0%, with the histopathological result as the gold standard. The AUC of the BALFilter Reader is 0.84 ± 0.08. Moreover, a customized Web was developed for a user-friendly interface and the promotion of wide applications. The current results revealed that the developed BALFilter Reader is a rapid, bias-free and easily accessible AI-enabled tool to promote the transplantation of the BALFilter technique. This work can easily expand to other cytopathological diagnoses and improve the application value of micro/nanotechnology-based liquid biopsy in the era of intelligent pathology.

The complexity of thermal management increases as integrated circuits evolved into 3D architectures. Because of the large variation that exists in the thermal conductivity of materials and the geometrical size of structures in the 3D-stacked IC (3D-SIC) network, the extensive computational costs typically render a full-chip-scale numerical simulation impossible. Thus, this paper proposes a fast and implementable full chip-scale numerical simulation method for thermal management of 3D-SIC. A compact thermal resistance network, with both lateral and vertical heat dissipations considered, is analyzed to establish an accurate anisotropic equivalent thermal conductivity model. The key heat dissipation component, the high thermal conduction path (HTCP) constructed using through-silicon vias (TSVs), micro-bumps, and Cu wires in the redistribution layer (RDL), is fully analyzed by modeling a compact thermal resistance network. The equivalent thermal conductivity of each stacked layer is extracted in blocks from the network and then applied in a finite element calculation for full-chip-scale numerical simulation. Three partitioning strategies to block each stacked layer are tested. As compared to the results of direct finite element simulation of a small-scale 3D-SIC, the proposed method yields improved simulation accuracy (temperature difference <7.5%) and a considerable computational cost reduction (grid number reduced by >77%). As a demonstration, the temperature distribution of a large-scale 3D-SIC with 306 TSVs and 1647 hotspots is successfully simulated within 82 min by implementing this method using a personal computer (Intel Core i5 6300HQ 60 GB memory). (C) 2017 Elsevier Ltd. All rights reserved.

Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.

With the rapid increment of the power density and the introduction of vertical stack, heat dissipation has become a challenge issue. Thermal-aware placement thereby attracts more and more attentions for 3D IC. Meanwhile, as the keep-going scaling-down of IC, a huge computation consumption was caused by the large scale span. In this paper, an equivalent anisotropic thermal conductivity model was introduced to low down the computation consumption caused by the huge feature size difference. Correctness of this model was verified and the deviation from a full-scale simulation was less than 20%. By applying this model, thermal distribution of a designed 3D IC with 1566 TSVs and 80504 hot-spots was obtained with the total computation time of about 24 minutes in a regular personal computer.

Thermal issue is becoming more and more serious when integrated circuits (IC) further explores along the road of More Moore with dramatic increments of integration degree and power density. Thermal management, including thermal design, modeling, and optimization, has been an important concern in the system-level design of 3D IC. Current thermal modeling for a system level 3D IC design usually relies on a simplified thermal resistance network, which requires trade-offs between the model complexity and the simulation accuracy. Comparing to traditional thermal resistance based model, finite element simulation can provide a more accurate simulation for the thermal management of 3D IC. However, a full chip scale numerical simulation is still lack as an unacceptable huge grid number is unavoidable to deal with the geometric size mismatch existed in a 3D IC. Moreover, current finite element method based numerical simulation tools have no direct supports for the thermal management of 3D IC, since the placement design usually consists a complex data structure from a 3D IC. A method to bridge the finite element method and the 3D IC placement is introduced in this work. The whole bridge process includes placement data structure extraction, 3D IC system model generation, structure, mesh, solver configuration, calculation, and post data analysis. A full chip scale numerical simulation was demonstrated based the present bridge method along with the recently reported equivalent thermal conductivity simplified model.